公开(公告)号：EP1461828A4

公开(公告)日：2005-09-28

申请号：EP02803310

申请日：2002-11-07

Applicant: IBM

Inventor： VOLANT RICHARD P ,  BISSON JOHN C ,  COTE DONNA R ,  DALTON TIMOTHY J ,  GROVES ROBERT A ,  PETRARCA KEVIN S ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

IPC: B81B3/00 ,  B81C1/00 ,  H01H49/00 ,  H01H59/00

CPC classification number: B81C1/00246 ,  B81B2201/016 ,  B81B2201/018 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0122 ,  B81C2203/0735 ,  H01G5/40 ,  H01H59/0009

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

公开(公告)号：EP2286444A4

公开(公告)日：2012-11-21

申请号：EP09747138

申请日：2009-04-28

Applicant: IBM

Inventor： ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

IPC: H01L23/525 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2250669A4

公开(公告)日：2012-07-25

申请号：EP09710899

申请日：2009-02-11

Applicant: IBM

Inventor： LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K ,  STEIN KENNETH J

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和由环形导体层包围的塞子层。 一种用于制造穿通基底通孔的方法，包括在基底内形成盲孔，并且在盲孔内依次形成并随后在盲孔内进行平坦化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。