公开(公告)号：EP2629320B1

公开(公告)日：2018-10-17

申请号：EP13155361.2

申请日：2013-02-15

申请人： IMEC VZW

发明人： Vincent, Benjamin ,  Thean, Aaron ,  Witters, Liesbeth

IPC分类号： H01L21/20 ,  H01L21/02 ,  H01L23/04 ,  H01L25/04 ,  H01L29/66 ,  C30B19/00 ,  C30B23/04 ,  C30B25/04 ,  C30B29/40

CPC分类号： H01L21/02639 ,  C30B19/00 ,  C30B19/12 ,  C30B23/04 ,  C30B25/04 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

摘要： The invention is related to a mask structure suitable for producing a defect free epitaxially grown structure of a crystalline material on substrate of another crystalline material, the two materials having difference lattice constants. The mask comprises two levels : a first level comprising a first layer provided with a first opening, for example of first trench, the bottom of which is formed by the substrate formed of the first material. The second level comprises at least a barrier placed on at least two opposite sides of the trench. According to a preferred embodiment, the second level comprises one or more second trenches arranged perpendicularly to the first trench. The depth and width of the first and second trenches is such that defects generated in the epitaxially grown layer of the second material at the substrate portion at the bottom of the first trench, and propagating in the direction of the second trenches are trapped in the first trench. In this way, in the larger portion of the second trenches, essentially defect free material can be grown.

公开(公告)号：EP3067919A1

公开(公告)日：2016-09-14

申请号：EP15158703.7

申请日：2015-03-11

申请人： IMEC VZW

发明人： Milenin, Alexey ,  Witters, Liesbeth

IPC分类号： H01L21/3065

CPC分类号： H01L21/3065 ,  H01L21/30655

摘要： Method for forming vertical structures in a semiconductor target layer comprising at least one element selected from the group consisting of Si and Ge, the said method comprising the steps of a) Providing a patterned hard mask layer on the semiconductor target layer; b) Dry plasma etching of the semiconductor target layer through said patterned hard mask, thereby forming said vertical structures. The said dry plasma etching comprises at least the steps of II. Halogen, with or without 02, based plasma etching or Fluorocarbon based plasma etching, III. Fluorocarbon based plasma etching when the step II. is a halogen based plasma etching or halogen based plasma etching when the step II. is a fluorocarbon based plasma etching, when the halogen based plasma etching is performed without 02, a step of 02 and/or N2 based passivation, step I. is performed before the plasma etching step II.

摘要翻译： 一种在半导体目标层中形成垂直结构的方法，包括从由Si和Ge组成的组中选择的至少一种元素，所述方法包括以下步骤：a）在半导体靶层上提供图案化的硬掩模层; b）通过所述图案化的硬掩模干燥等离子体蚀刻半导体靶层，从而形成所述垂直结构。 所述干等离子体蚀刻至少包括以下步骤：II。 卤素，有或没有O2，基于等离子体蚀刻或基于氟碳的等离子体蚀刻，III。 基于氟碳的等离子体蚀刻步骤II。 是基于卤素等离子体蚀刻或卤素等离子体蚀刻时的步骤II。 是基于碳氟化合物的等离子体蚀刻，当在不进行氧化物的情况下进行卤素等离子体蚀刻时，在等离子体蚀刻步骤II之前执行步骤I 2和/或N 2的钝化步骤I.

公开(公告)号：EP2978016B1

公开(公告)日：2018-06-13

申请号：EP14178560.0

申请日：2014-07-25

申请人： IMEC VZW

发明人： Loo, Roger ,  Mitard, Jerome ,  Witters, Liesbeth

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/02

CPC分类号： H01L27/0922 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

摘要： A method for providing an nMOS device and a pMOS device on a silicon substrate, comprising: a. providing trenches in a dielectric layer on the silicon substrate, at least a first trench defining an nMOS region and a second trench defining a pMOS region, the trenches extending through the dielectric layer and abutting a surface of the substrate; b. growing a first seed layer in the first trench on the surface; c. growing a common strain relaxed buffer layer in the first and the second trench, the strain relaxed buffer layer comprising silicon germanium; d. growing a common channel layer comprising germanium (Ge) in the first trench and the second trench on the common strain relaxed buffer layer; wherein the properties of the first seed layer an the common strained relaxed buffer layer are predetermined such that the common channel layer comprises tensile strain or is unstrained in the nMOS region and comprises compressive strain in the pMOS region; and associated substrate.

公开(公告)号：EP2908345A1

公开(公告)日：2015-08-19

申请号：EP14154933.7

申请日：2014-02-13

申请人： IMEC VZW

发明人： Milenin, Alexey ,  Witters, Liesbeth

IPC分类号： H01L29/417 ,  H01L29/66

CPC分类号： H01L21/32051 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

摘要： A process for creating a contact on a Ge-containing contact region (3) of a semiconductor structure (9), said process comprising the steps of:
-Providing said semiconductor structure (9) comprising:
i. A Ge-containing contact region (3),
ii. Optionally, a SiO 2 layer (5) coating said Ge-containing contact region (3),
iii. A Si 3 N 4 layer (6) coating said SiO 2 layer (5) if present or said Ge-containing contact region (3),

-Etching selectively the Si 3 N 4 layer (6) by means of an inductively coupled plasma, thereby exposing the underlying SiO 2 layer (5) if present or the Ge-containing contact region (3),
-Etching selectively the SiO 2 layer (5) if present, thereby exposing the SiGe:B contact region (3), and
-Creating said contact on said Ge-containing contact region (3).

摘要翻译： 一种用于在半导体结构（9）的含Ge接触区域（3）上形成接触的方法，所述方法包括以下步骤： - 提供所述半导体结构（9），包括：i。 含锗接触区域（3），ii。 任选地，涂覆所述含Ge接触区域（3）的SiO 2层（5），iii。 涂覆所述SiO 2层（5）的Si 3 N 4层（6）或所述含锗接触区域（3），通过电感耦合等离子体选择性地选择性地形成Si 3 N 4层（6） 如果存在下面的SiO 2层（5）或Ge含有接触区域（3），则选择性地选择性地选择SiO 2层（5），从而暴露SiGe：B接触区域（3） 在所述含Ge接触区域（3）上形成所述接触。

公开(公告)号：EP2704199B1

公开(公告)日：2020-01-01

申请号：EP12182800.8

申请日：2012-09-03

申请人： IMEC VZW ,  Taiwan Semiconductor Manufacturing Company, Limited

发明人： Witters, Liesbeth ,  Vos, Rita ,  Brunco, David ,  Van Dal, Marcus

IPC分类号： H01L29/165 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/285

公开(公告)号：EP2978016A1

公开(公告)日：2016-01-27

申请号：EP14178560.0

申请日：2014-07-25

申请人： IMEC VZW

发明人： Loo, Roger ,  Mitard, Jerome ,  Witters, Liesbeth

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/10

CPC分类号： H01L27/0922 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

摘要： A method for providing an nMOS device and a pMOS device on a silicon substrate, comprising:
a. providing trenches in a dielectric layer on the silicon substrate, at least a first trench defining an nMOS region and a second trench defining a pMOS region, the trenches extending through the dielectric layer and abutting a surface of the substrate;
b. growing a first seed layer in the first trench on the surface;
c. growing a common strain relaxed buffer layer in the first and the second trench, the strain relaxed buffer layer comprising silicon germanium;
d. growing a common channel layer comprising germanium (Ge) in the first trench and the second trench on the common strain relaxed buffer layer;
wherein the properties of the first seed layer an the common strained relaxed buffer layer are predetermined such that the common channel layer comprises tensile strain or is unstrained in the nMOS region and comprises compressive strain in the pMOS region; and associated substrate.

摘要翻译： 一种用于提供到NMOS器件和PMOS器件上的硅衬底的方法，包括：一个。 在硅衬底的沟槽提供在介电层，至少一个第一NMOS区域和沟槽限定了第二沟槽限定PMOS区域，所述沟槽穿过介电层延伸并邻接所述基片的表面上; 湾 在生长表面上的第一沟槽的第一籽晶层; 温度。 生长在第一和第二沟槽，所述应变驰豫缓冲层包括硅锗的共同应变松弛缓冲层; 天。 生长在所述第一沟槽和所述公共应变松弛缓冲层上的第二沟槽的公共信道层，其包含锗（Ge）; worin共同应变驰豫缓冲层上的第一籽晶层的特性正在寻求预定做的公共信道层包括拉伸应变或是在nMOS区域无应变，并包括在PMOS区域压缩应变; 和相关联的基材。

公开(公告)号：EP3171409A1

公开(公告)日：2017-05-24

申请号：EP15195235.5

申请日：2015-11-18

申请人： IMEC VZW

发明人： Demuynck, Steven ,  Tao, Zheng ,  Chan, Boon Teik ,  Witters, Liesbeth ,  Schaekers, Marc ,  Peter, Antony Premkumar ,  Armini, Silvia

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/02115 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785

摘要： A method for fabricating a semiconductor structure, the method comprising providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

摘要翻译： 一种用于制造半导体结构的方法，该方法包括：提供图案化衬底，其包括一个半导体区域和电介质区域。 第一介电材料的共形层被直接沉积在图案化的基板。 牺牲材料的层沉积覆盖所述第一介电材料的共形层。 牺牲材料被图案化，从而使半导体区域的一部分处于被构图的牺牲材料覆盖。 一第二介电材料层沉积在图案化衬底，从而完全呼叫覆盖构图的牺牲材料。 甲凹部设置在所述第二电介质材料通过完全呼叫去除所述构图的牺牲材料而形成。 第一介电材料的露出共形层被选择性地去除所述半导体区域。

公开(公告)号：EP3016143A1

公开(公告)日：2016-05-04

申请号：EP14191340.0

申请日：2014-10-31

申请人： IMEC VZW

发明人： Collaert, Nadine ,  Eneman, Geert ,  Horiguchi, Naoto ,  Kim, Min-Soo ,  Rooyackers, Rita ,  Veloso, Anabela ,  Witters, Liesbeth

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

摘要： A method for forming a transistor structure comprising a fin-shaped channel structure, comprising:
- providing a layer stack embedded laterally in STI structures;
- recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion;
- providing one or more protection layers on the upper portion of the layer stack;
- after providing one or more protection layers, further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack;
- removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other;
wherein providing the layer stack comprises providing an etch stop layer at a position directly below the channel portion, such that the freestanding upper part of the layer stack comprises an etch stop layer at its lower surface after selectively removing the central portion.

摘要翻译： 一种用于形成包括鳍状沟道结构的晶体管结构的方法，包括：提供在STI结构中横向嵌入的层堆叠; - 将STI结构凹陷到层堆叠附近，从而暴露层堆叠的上部，上部至少包括通道部分; - 在所述层堆叠的上部提供一个或多个保护层; - 在提供一个或多个保护层之后，进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分; - 去除层堆叠的中心部分，导致层堆叠的独立上部和下部在物理上彼此分离; 其中提供层堆叠包括在通道部分正下方的位置处提供蚀刻停止层，使得层堆叠的独立上部在选择性地去除中心部分之后在其下表面处包含蚀刻停止层。

公开(公告)号：EP2849219A1

公开(公告)日：2015-03-18

申请号：EP13183985.4

申请日：2013-09-11

申请人： IMEC VZW

发明人： Waldron, Niamh ,  Witters, Liesbeth

IPC分类号： H01L21/8258 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/04

CPC分类号： H01L27/0922 ,  H01L21/762 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/20 ,  H01L29/267

摘要： A method for manufacturing a CMOS device, comprising providing a starting substrate, the starting substrate comprising a silicon substrate the surface of which is oriented along the (100) crystal plane;
- forming shallow trench isolation structures in a first predetermined region, thereby defining channel areas in said substrate embodied as silicon protrusions extending from said silicon substrate and being isolated from each other by means of isolation structures;
- removing said silicon protrusions, thereby creating trenches;
- filling said trenches by epitaxially growing a III-V material in said trenches, to thereby form channel structures of transistors of a first type which are essentially defect-free; and associated substrate.

摘要翻译： 一种制造CMOS器件的方法，包括提供起始衬底，所述起始衬底包括硅衬底，所述衬底的表面沿（100）晶面定向; - 在第一预定区域中形成浅沟槽隔离结构，从而限定所述衬底中的通道区域，其被实施为从所述硅衬底延伸并通过隔离结构彼此隔离的硅突起; - 去除所述硅突起，从而产生沟槽; - 通过在所述沟槽中外延生长III-V材料来填充所述沟槽，从而形成基本上无缺陷的第一类晶体管的沟道结构; 和相关底物。

公开(公告)号：EP2819154A1

公开(公告)日：2014-12-31

申请号：EP13173380.0

申请日：2013-06-24

申请人： IMEC VZW ,  Samsung Electronics Co., Ltd.

发明人： Lee, Seung Hun ,  Witters, Liesbeth ,  Loo, Roger

IPC分类号： H01L21/762

CPC分类号： H01L21/02658 ,  H01L21/02587 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/1054

摘要： The present invention relates to a method (100) for forming a strained semiconductor structure (212, 312). The method comprises providing (102) a strain relaxed buffer layer (204), forming (104) a sacrificial layer (206, 306) on said strain relaxed buffer layer (204), forming (106) a shallow trench isolation structure (208) through said sacrificial layer (206, 306), removing (108) at least a portion (210) of an oxide layer on said sacrificial layer (206, 306), etching (110) through said sacrificial layer (206, 306) such that a portion of said strain relaxed buffer layer (204) is exposed (110), forming said strained semiconductor structure (212, 312) on said exposed portion (210) of said strain relaxed buffer layer (204).

摘要翻译： 本发明涉及一种用于形成应变半导体结构（212,312）的方法（100）。 该方法包括提供（102）应变松弛缓冲层（204），在所述应变松弛缓冲层（204）上形成（104）牺牲层（206,306），形成（106）浅沟槽隔离结构（208） 通过所述牺牲层（206,306），去除（108）所述牺牲层（206,306）上的氧化物层的至少一部分（210），通过所述牺牲层（206,306）蚀刻（110），使得 所述应变松弛缓冲层（204）的一部分被暴露（110），在所述应变松弛缓冲层（204）的所述暴露部分（210）上形成所述应变半导体结构（212,312）。