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    A SEMICONDUCTOR COMPONENT COMPRISING BACK SIDE I/O SIGNAL ROUTING
    2.
    发明公开
    A SEMICONDUCTOR COMPONENT COMPRISING BACK SIDE I/O SIGNAL ROUTING 审中-公开

    公开(公告)号：EP4187600A1

    公开(公告)日：2023-05-31

    申请号：EP21210849.2

    申请日：2021-11-26

    申请人： Imec VZW

    发明人： Chen, Shih-Hung ,  Beyne, Eric ,  Van der Plas, Geert

    IPC分类号： H01L27/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

    摘要： The invention is related to a semiconductor component, for example an integrated circuit chip, comprising a semiconductor substrate (1) having active devices (7) at the front side thereof and I/O terminals (19) at the back side of the component. The terminals are connected to the active devices through TSV connections (16b) and buried rails (15b) in an area (5) of the substrate that is separate from the area (4) in which the active devices are located. According to the invention, the I/O TSV connections (16b) are located in a floating well (25) of the substrate that is separated from the rest of the substrate by a second well (26) formed of material of the opposite conductivity type compared to the material of the floating well. The second well (26) comprises at least one contact (28) configured to be coupled to a voltage that is suitable for reverse-biasing the junction (27) between the floating well (25) and the second well (26). In this way, a small capacitance is placed in series with the large parasitic capacitance generated by a thin dielectric liner that isolates the I/O TSVs and I/O rails from the substrate, thereby mitigating the negative effect of the large parasitic capacitance. According to preferred embodiments, additional contacts and conductors are provided which are configured to create an ESD protection circuit for protecting the I/O TSVs (16b) and the I/O rails (15b) from electrostatic discharges.

    AN INTEGRATED CIRCUIT CHIP WITH POWER DELIVERY NETWORK ON THE BACKSIDE OF THE CHIP
    6.
    发明公开
    AN INTEGRATED CIRCUIT CHIP WITH POWER DELIVERY NETWORK ON THE BACKSIDE OF THE CHIP 审中-公开

    公开(公告)号：EP3324436A1

    公开(公告)日：2018-05-23

    申请号：EP17196921.5

    申请日：2017-10-17

    申请人： IMEC vzw

    发明人： Beyne, Eric ,  Ryckaert, Julien

    IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/535

    摘要： In an IC according to the invention, power and ground rails are incorporated in the front end of line (FEOL). These power and ground rails are at the same level as the active devices and are therefore buried deep in the IC, as seen from the front of the chip. The connection from the buried interconnects to the source and drain areas is established by so-called 'local interconnects'. These local interconnects are not part of the back end of line, but they are for the most part embedded in a pre-metal dielectric layer onto which the BEOL is produced. Further according to the invention, the power delivery network of the IC is located in its entirety on the backside of the chip. The PDN is connected to the buried interconnects through suitable connections, for example metal-filled vias of the type known as 'through-semiconductor vias' or 'through silicon vias' (TSV). The invention is equally related to methods for producing an IC according to the invention.

    QUANTUM BIT CHIP WITH STACKED WAFERS AND METHOD FOR FABRICATION THEREOF
    8.
    发明公开
    QUANTUM BIT CHIP WITH STACKED WAFERS AND METHOD FOR FABRICATION THEREOF 审中-公开

    公开(公告)号：EP4195283A1

    公开(公告)日：2023-06-14

    申请号：EP21213080.1

    申请日：2021-12-08

    申请人： Imec VZW

    发明人： Derakhshandeh, Jaber ,  Radu, Iuliana ,  Beyne, Eric ,  Govoreanu, Bogdan

    IPC分类号： H01L27/18 ,  H01L23/00 ,  H01L25/065 ,  G06N10/40

    摘要： A quantum bit (qubit) chip (10) is disclosed which comprises two or more qubit wafers (11, 13), preferably having a thickness less than 1 μm, and one or more spacer elements (12, 14) which are alternately arranged along a common axis, and a conductive arrangement (15) electrically connecting the qubit wafers. The conductive arrangement (15) comprises at least one superconducting (SC) via per qubit wafer and spacer element, the SC via(s) passing through the respective qubit wafer or spacer element, preferably in form of a SC nano through-silicon-via (nTSV). A corresponding fabrication method is also disclosed.