公开(公告)号：EP2287905A3

公开(公告)日：2016-06-22

申请号：EP10250964.3

申请日：2010-05-24

申请人： Kabushiki Kaisha Toshiba

发明人： Takagi, Kazutaka

IPC分类号： H01L23/64 ,  H01L23/66 ,  H01L25/065 ,  H01L29/417 ,  H01L29/423 ,  H03F3/21 ,  H03F3/195 ,  H03F3/60

CPC分类号： H01L23/66 ,  H01L23/642 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/7787 ,  H01L2223/6627 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/1461 ,  H01L2924/1903 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H03F3/195 ,  H03F3/604 ,  H03F2200/255 ,  H03F2200/366 ,  H03F2200/408 ,  H03F2200/423 ,  H03F2200/543 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： According to one embodiment of the present invention, there is a high frequency circuit having a multi-chip module structure, including a semiconductor substrate set formed with discrete transistors connected in series, a first dielectric substrate set formed with capacitors, and a second dielectric substrate set formed with strip lines.

公开(公告)号：EP2911236A1

公开(公告)日：2015-08-26

申请号：EP14177873.8

申请日：2014-07-21

申请人： Kabushiki Kaisha Toshiba

发明人： Takagi, Kazutaka

IPC分类号： H01P5/107 ,  H01L23/66

CPC分类号： H01P3/08 ,  H01L23/66 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/1423 ,  H01L2924/15151 ,  H01L2924/1903 ,  H01P5/107 ,  H05K1/0237 ,  H05K1/115 ,  H05K1/181 ,  H01L2924/00012

摘要： Certain embodiments provide a millimeter wave bands semiconductor device including a metal base body, a circuit board, and a metal cover body. The base body has a first penetration hole and a second penetration hole. The circuit board is disposed on the base body and has an input signal line and an output signal line on a front side surface thereof. The cover body is disposed on the circuit board and has a first non-penetration hole and a second non-penetration hole. The cover body is disposed such that the first non-penetration hole is disposed directly above the first penetration hole of the base body and the second non-penetration hole is disposed directly above the second penetration hole of the base body. Further, the first non-penetration hole and the first penetration hole constitute a first waveguide and the second non-penetration hole and the second penetration hole constitute a second waveguide.

摘要翻译： 某些实施例提供了一种毫米波段半导体器件，其包括金属基体，电路板和金属盖体。 基体具有第一贯穿孔和第二贯穿孔。 电路板设置在基体上并且在其前侧表面上具有输入信号线和输出信号线。 盖体设置于电路板上并具有第一非贯穿孔及第二非贯穿孔。 盖体被配置为，第一非贯通孔配置在基体的第一贯通孔的正上方，第二非贯通孔配置在基体的第二贯通孔的正上方。 此外，第一非贯通孔和第一贯通孔构成第一波导，第二非贯通孔和第二贯通孔构成第二波导。

公开(公告)号：EP2428989A3

公开(公告)日：2015-07-29

申请号：EP11169866.8

申请日：2011-06-14

申请人： Fujitsu Limited

发明人： Masuda, Satoshi

IPC分类号： H01L23/057 ,  H01L23/66 ,  H01L23/498 ,  H01P1/04 ,  H01P5/02 ,  H01P3/00

CPC分类号： H01L23/057 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/66 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/166 ,  H01L2924/167 ,  H01L2924/16787 ,  H01L2924/1903 ,  H01L2924/19033 ,  H01L2924/19039 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01P3/006 ,  H01P5/028 ,  H01L2924/00

摘要： A high-frequency circuit package including a dielectric substrate (10); a signal line (31), a first ground conductor layer (32), a second ground conductor layer (33), and a frame-shaped dielectric layer (16) formed on the dielectric substrate; a fourth ground conductor layer (35) formed on the frame-shaped dielectric layer; a first recess (29) formed in the frame-shaped dielectric layer and including a first (29b) surface and a second surface (29c) that are located above the first ground conductor layer (32) and the second ground conductor layer (33) and extend laterally at an oblique angle with respect to the length direction of the signal line; a first ground line (38a) formed on the first surface and electrically connecting the second ground conductor layer (33) with the fourth ground conductor layer (35); and a second ground line (38b) formed on the second surface and electrically connecting the third ground conductor layer (34) with the fourth ground conductor layer (35).

公开(公告)号：EP2485253A4

公开(公告)日：2015-01-07

申请号：EP10820447

申请日：2010-09-24

申请人： KYOCERA CORP

发明人： TSUJINO MAHIRO ,  KINOSHITA MAMORU ,  MIYAWAKI KIYOSHIGE

IPC分类号： H01L23/02 ,  H01L23/04 ,  H01L23/057 ,  H01L23/552 ,  H01L23/66 ,  H01P1/00 ,  H01P1/04 ,  H01P5/02

CPC分类号： H01P5/022 ,  H01L23/057 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L24/48 ,  H01L2223/6627 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1903 ,  H01L2924/19051 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01P5/028 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A device housing package (1) includes a substrate (3) having a device (2) mounting region (R) in an upper face thereof; and a frame body (4) having a through hole (H) formed in part thereof, the frame body being disposed on the substrate (3) so as to lie along a periphery of the device mounting region (R). The device housing package (1) includes an input-output terminal (5) disposed in the through hole (H), the input-output terminal having a first dielectric layer (7) extending interiorly and exteriorly of the frame body (4); a signal line (8) formed on the first dielectric layer (7) and configured to provide electrical connection between an interior of the frame body (4) and an exterior thereof; a first ground layer (9a) formed on a lower face of the first dielectric layer (7); a second dielectric layer (10) formed on the signal line (8) so as to overlap the frame body (4) as viewed in a transparent plan view; a second ground layer (9b) formed on an upper face of the second dielectric layer (10); and a metal layer (11) disposed within the second dielectric layer (10) so as to extend from the interior of the frame body (4) to the exterior thereof along the signal line (8). The metal layer (11) is formed to extend from the second dielectric layer (10) to the first dielectric layer (7), being separated from the signal line (8).

公开(公告)号：EP1152485B1

公开(公告)日：2014-06-18

申请号：EP00902973.7

申请日：2000-02-15

申请人： National Institute of Information and Communications Technology ,  Sharp Kabushiki Kaisha ,  Matsui, Toshiaki

发明人： MATSUI, Toshiaki ,  YAMADA, Atsushi

IPC分类号： H01Q1/38 ,  H01Q1/42 ,  H01Q13/10 ,  H01Q13/18 ,  H01Q19/06 ,  H01Q23/00 ,  H01L23/66

CPC分类号： H01Q23/00 ,  H01L2223/6627 ,  H01L2224/16225 ,  H01L2924/1903 ,  H01Q1/42 ,  H01Q13/10 ,  H01Q19/062

公开(公告)号：EP2609623A2

公开(公告)日：2013-07-03

申请号：EP11752370.4

申请日：2011-08-04

申请人： Oracle International Corporation

发明人： HARADA, John A. ,  DOUGLAS, David C. ,  DROST, Robert J.

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  G02B6/43 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/6627 ,  H01L2224/131 ,  H01L2224/14155 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/1903 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/014

摘要： A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a stepped terrace. A high-bandwidth ramp component, which is positioned approximately parallel to the stepped terrace, is mechanically coupled to the semiconductor dies. Furthermore, the ramp component includes an optical waveguide that conveys the optical signal, and an optical coupling component that optically couples the optical signal to one of the semiconductor dies, thereby facilitating high-bandwidth communication of the optical signal between the semiconductor die and the ramp component.

公开(公告)号：EP2451254B1

公开(公告)日：2013-04-17

申请号：EP12151874.0

申请日：2005-02-24

申请人： BelAir Networks Inc.

发明人： Brunette, Gilbert P. ,  Johnson, Eric ,  Rayment, Stephen G. ,  Soul, Colin

IPC分类号： H05K1/02

CPC分类号： H05K1/0251 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/1903 ,  H05K1/0222 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

公开(公告)号：EP2290687A1

公开(公告)日：2011-03-02

申请号：EP09168873.9

申请日：2009-08-27

申请人： NXP B.V.

发明人： Thoonen, Hendrikus Johannes Jacobus ,  Buot, Rey ,  Nunn, Wayne ,  van Mil, Job ,  van Straten, Freek Egbert

IPC分类号： H01L23/66 ,  H01L23/64 ,  H01L23/498

CPC分类号： H01L23/645 ,  H01L23/49816 ,  H01L23/64 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6627 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1903 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method (200) of designing a packaged integrated circuit (100), wherein the method comprises determining (202) an electric model of the packaged integrated circuit (100), analyzing (206) a characteristic of a transmission of an electric signal by the packaged integrated circuit (100) based on the electric model, and modifying (210) the packaged integrated circuit (100) based on a result of the analyzing (206) for reducing discontinuities of a characteristic impedance of the packaged integrated circuit (100).

摘要翻译： 一种设计封装集成电路（100）的方法（200），其中所述方法包括确定（202）所述封装集成电路（100）的电模型，分析（206）所述电信号的传输特性 基于电气模型的封装集成电路（100），以及基于用于减少封装集成电路（100）的特性阻抗的不连续性的分析结果（206）修改（210）封装集成电路（100）。

公开(公告)号：EP2284888A2

公开(公告)日：2011-02-16

申请号：EP10008048.0

申请日：2010-08-02

申请人： Sony Corporation

发明人： Akiba, Akira ,  Mitarai, Shun ,  Ikeda, Koichi ,  Morita, Shinya

IPC分类号： H01L23/66 ,  H01Q1/38 ,  H01Q23/00 ,  H01Q1/22 ,  H01L23/498

CPC分类号： H01L23/66 ,  H01L23/13 ,  H01L23/147 ,  H01L23/645 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12034 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/157 ,  H01L2924/1903 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01Q1/38 ,  H01Q19/24 ,  H01Q19/30 ,  H05K1/024 ,  H05K1/141 ,  H05K1/16 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/20752

摘要： An interposer with which the manufacturing steps are able to be simplified and which shows superior high frequency characteristics is provided. The interposer includes: a substrate having a front face and a rear face; a wiring that is formed on the front face side of the substrate and is electrically connected to a semiconductor chip; an electric device connected to the wiring; and a concave section that is formed from the rear face side of the substrate in a position corresponding to the electric device.

摘要翻译： 提供了能够简化制造步骤并且显示出优异的高频特性的插入器。 所述插入件包括：具有正面和背面的基板; 形成在基板的正面侧并与半导体芯片电连接的布线; 连接到布线的电气设备; 以及从与所述电气装置对应的位置从所述基板的背面侧形成的凹部。

公开(公告)号：EP1444733B1

公开(公告)日：2010-12-01

申请号：EP02795072.4

申请日：2002-10-25

申请人： International Business Machines Corporation

发明人： ALCOE, Dave ,  NOWAK, Ronald ,  PREDA, Francesco ,  OGGIONI, Stefano, Sergio

IPC分类号： H01L23/498

CPC分类号： H05K1/0219 ,  H01L23/16 ,  H01L23/36 ,  H01L23/49822 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01057 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/111 ,  H05K2201/09236 ,  H05K2201/09781

摘要： An electronic device carrier (110) adapted for transmitting high-frequency signals, including a circuitized substrate with a plurality of conductive layers (240a to 240g) insulated from each other, the conductive layers being arranged in a sequence from a first one of the conductive layers (240a) wherein a plurality of signal tracks (200) each one ending with a contact area (205) for transmitting a high-frequency signal are formed, and a reference structure (215a, 215b, 230) connectable to a reference voltage or ground for shielding the signal tracks the reference structure includes at least one reference track (230) formed in a second one of the conductive layers (240b) adjacent to the first conductive layer and at least one further refer­ence track formed in one of the conductive layers (240d) different from the first and second conductive layer, a portion of each signal track excluding at least the area corresponding to the orthographic projection of associated contact area being superimposed in plan view to a corre­sponding reference track and at least a part of the area corresponding to the orthographic projection of the contact area associated to each signal track being superimposed in plan view to a corresponding further reference track with interposition of a floating conductive track, i.e. a track not connected to any signal, reference voltage or ground track.