公开(公告)号：EP3183752A4

公开(公告)日：2018-03-21

申请号：EP14900215

申请日：2014-08-19

申请人： INTEL CORP

发明人： JAN CHIA HONG ,  HAFEZ WALID ,  CHANG HSU YU ,  OLAC VAW ROMAN ,  CHANG TING ,  RAMASWAMY RAHUL ,  LIU PEI CHI ,  DIAS NEVILLE

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/49

CPC分类号： H01L29/42376 ,  H01L21/28088 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823475 ,  H01L23/535 ,  H01L23/66 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

摘要： Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

公开(公告)号：EP3158586A4

公开(公告)日：2018-01-17

申请号：EP14895422

申请日：2014-06-20

申请人： INTEL CORP

发明人： PHOA KINYIP ,  NIDHI NIDHI ,  JAN CHIA-HONG ,  CHANG TING

IPC分类号： H01L29/78 ,  H01L21/335 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/7834 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/66621 ,  H01L29/7835

摘要： High voltage transistors spanning multiple non-planar semiconductor bodies, such as fins or nanowires, are monolithically integrated with non-planar transistors utilizing an individual non-planar semiconductor body. The non-planar FETs may be utilized for low voltage CMOS logic circuitry within an IC, while high voltage transistors may be utilized for high voltage circuitry within the IC. A gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device. The high voltage channel region may be a planar length of substrate recessed relative to the fins. A high voltage gate stack may use an isolation dielectric that surrounds the fins as a thick gate dielectric. A high voltage transistor may include a pair of doped wells formed into the substrate that are separated by the high voltage gate stack with one or more fin encompassed within each well.

公开(公告)号：EP3183751A4

公开(公告)日：2018-03-28

申请号：EP14900011

申请日：2014-08-19

申请人： INTEL CORP

发明人： OLAC VAW ROMAN ,  HAFEZ WALID ,  JAN CHIA HONG ,  CHANG HSU YU ,  CHANG TING ,  RAMASWAMY RAHUL ,  LIU PEI CHI ,  DIAS NEVILLE

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L21/768 ,  H01L27/11206 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.

公开(公告)号：EP3161871A4

公开(公告)日：2018-02-21

申请号：EP14896226

申请日：2014-06-27

申请人： INTEL CORP

发明人： DIAS NEVILLE L ,  JAN CHIA-HONG ,  HAFEZ WALID M ,  OLAC-VAW ROMAN W ,  CHANG HSU-YU ,  CHANG TING ,  RAMASWAMY RAHUL ,  LIU PEI-CHI

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/417 ,  H03D7/14 ,  H03D7/16

CPC分类号： H01L29/7853 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H03D7/1425 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/165

摘要： An embodiment includes an apparatus comprising: a non-planar fm having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one fmFET. Other embodiments are described herein.

公开(公告)号：EP3123509A4

公开(公告)日：2017-11-22

申请号：EP14887643

申请日：2014-03-24

申请人： INTEL CORP

发明人： CHANG TING ,  JAN CHIA-HONG ,  HAFEZ WALID M

IPC分类号： H01L23/62 ,  G11C17/16 ,  G11C29/04 ,  H01L23/525 ,  H01L27/102 ,  H01L27/112

CPC分类号： H01L23/5252 ,  G11C17/143 ,  G11C17/16 ,  G11C17/165 ,  H01L23/62 ,  H01L27/1021 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1 T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.