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19 条记录 (耗时 0.012 秒)

    Precision metal-metal capacitor for analog circuit
    3.
    发明公开
    Precision metal-metal capacitor for analog circuit 失效
    PräzisionskondensatorMetall-Metallfüranaloge Schaltung

    公开(公告)号：EP0771022A2

    公开(公告)日：1997-05-02

    申请号：EP96306961.2

    申请日：1996-09-25

    申请人： International Business Machines Corporation

    发明人： Brabazon, Terry J. ,  El-Kareh, Badih ,  Martin, Stuart R. ,  Rutten, Matthew Jeremy ,  Kaanta, Carter Welling

    IPC分类号： H01L21/3205

    CPC分类号： H01L28/40 ,  H01L21/76895

    摘要： A precision analog metal-metal capacitor is fabricated by forming a first capacitor plate in an insulation layer by forming a trench therein, depositing metal within the trench and planarizing the device. A thin dielectric layer is then deposited and patterned over the first capacitor plate. A second insulator is then deposited over the device and discrete openings etched therein to expose the insulation layer and first metal plate. Metal is deposited within the openings and planarized, thereby forming a contact to the first metal plate and the second metal plate of the capacitor.

    摘要翻译： 通过在绝缘层中形成第一电容器板，在其中形成沟槽，在沟槽内沉积金属并对器件进行平坦化，制造精密模拟金属 - 金属电容器。 然后在第一电容器板上沉积并图案化薄的电介质层。 然后将第二绝缘体沉积在器件上并且在其中蚀刻的离散开口露出绝缘层和第一金属板。 金属沉积在开口内并平坦化，从而形成与电容器的第一金属板和第二金属板的接触。

    Low voltage programmable storage element
    4.
    发明公开
    Low voltage programmable storage element 失效
    Spanung计划小姐Speicherelement。

    公开(公告)号：EP0511560A2

    公开(公告)日：1992-11-04

    申请号：EP92106611.4

    申请日：1992-04-16

    申请人： International Business Machines Corporation

    发明人： Abadeer, Wagdi William ,  El-Kareh, Badih ,  Ellis, Wayne Frederick ,  Galbi, Duane Elmer ,  Hiltebeitel, Nathan Rafael ,  Tonti, William Robert ,  Watts, Josef Samuel

    IPC分类号： G11C17/14 ,  G11C17/16

    CPC分类号： G11C29/785 ,  G11C17/14 ,  G11C17/16

    摘要： A programmable storage element for redundancy-programming includes a programmable antifuse circuit which includes a plurality of first resistors (F1a, F1b, F1c) and a switching circuit (Q Fa , Q Fb , Q Fc , Q Fd ) for coupling the first resistors in series in response to a plurality of first control signals (Ta, Tb, Tc, Td) and for coupling the first resistors in parallel in response to a plurality of second control signals to permit programming of the first resistors, and a sensing circuit for determining whether or not the first resistors have been programmed. The state of the first resistors is determined by comparing a first voltage drop across the first resistors with a second voltage drop across a second resistor. Each of the first resistors is an unsilicided polysilicon conductor which has an irreversible resistance decrease when a predetermined threshold current is applied for a minimum period of time.

    摘要翻译： 用于冗余编程的可编程存储元件包括可编程反熔丝电路，其包括多个第一电阻器（F1a，F1b，F1c）和用于响应于第一电阻器串联耦合第一电阻器的开关电路（QFa，QFb，QFc，QFd） 多个第一控制信号（Ta，Tb，Tc，Td），并且用于响应于多个第二控制信号并联耦合第一电阻器以允许编程第一电阻器;以及感测电路，用于确定是否 第一个电阻已编程。 第一电阻器的状态通过将第一电阻器两端的第一电压降与第二电阻器上的第二电压降进行比较来确定。 第一电阻器中的每一个是非极性多晶硅导体，当预定阈值电流施加最小时间时，其具有不可逆电阻降低。

    Multi-layer interconnect for integrated circuit
    7.
    发明公开
    Multi-layer interconnect for integrated circuit 失效
    Mehrschicht-Verbindungfürintegrierte Schaltung

    公开(公告)号：EP0809290A3

    公开(公告)日：2000-05-17

    申请号：EP97303230.3

    申请日：1997-05-12

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： El-Kareh, Badih ,  Ryan, James E.

    IPC分类号： H01L23/522

    CPC分类号： H01L28/40 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/53223 ,  H01L23/53228 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

    摘要： A metal interconnect having a high conductivity and high resistance to metal migration failure is formed of two layers of metal or alloy (15,17) (such as TI/CuAlSi) with a dielectric (16) interposed therebetween and a connection made between the layers (15,17) by a conductive material, preferably in the form of a plug or stud (14) formed in an aperture of an inter-level dielectric, at ends of the interconnect. A high precision metal-to-metal capacitor can be formed from the same layers (15,17) by forming separate connections to each of the layers. The topography of the interconnect (and capacitor) is of reduced severity and facilitates planarization of an overlying inter-level dielectric.

    摘要翻译： 具有高导电性和高金属迁移破坏性的金属互连由两层金属或合金（例如TI / cuAlsi）形成，其间插有电介质，并且通过导电材料形成在该层之间的连接，优选在 形成在互连的端部处形成在级间电介质的孔中的插头或螺柱的形式。 通过形成与每个层的分离的连接，可以从相同的层形成高精度金属 - 金属电容器。 互连（和电容器）的形貌具有降低的严重性，并且有助于覆盖层间电介质的平坦化。

    Method for dual gate oxide dual workfunction CMOS
    8.
    发明公开
    Method for dual gate oxide dual workfunction CMOS 审中-公开
    Verfahrenfüreinen CMOS mit zweifachem Gateoxid und zweifacher Austrittsarbeit

    公开(公告)号：EP0935285A1

    公开(公告)日：1999-08-11

    申请号：EP99300234.4

    申请日：1999-01-14

    申请人： International Business Machines Corporation

    发明人： Bronner, Gary Bela ,  El-Kareh, Badih ,  Schuster, Stanley Everett

    IPC分类号： H01L21/8239 ,  H01L21/8238

    CPC分类号： H01L27/10873 ,  H01L21/823842

    摘要： A method of forming integrated circuit chips including two dissimilar type NFETs and/or two dissimilar type PFETs on the same chip, such as both thick and thin gate oxide FETs. A DRAM array may be constructed of the thick oxide FETs and logic circuits may be constructed of the thin oxide FETs on the same chip. First, a gate stack including a first, thick gate SiO2 layer is formed on a wafer. The stack includes a doped polysilicon layer on the gate oxide layer, a silicide layer on the polysilicon layer and a nitride layer on the silicide layer. Part of the stack is selectively removed to re-expose the wafer where logic circuits are to be formed. A thinner gate oxide layer is formed on the re-exposed wafer. Next, gates are formed on the thinner gate oxide layer and thin oxide NFETs and PFETs are formed at the gates. After selectively siliciding thin oxide device regions, gates are etched from the stack in the thick oxide device regions. Finally, source and drain regions are implanted and diffused for the thick gate oxide devices.

    摘要翻译： 在同一芯片上形成包括两个不同类型的NFET和/或两个不同类型的PFET的集成电路芯片的方法，例如厚的和薄的栅极氧化物FET。 DRAM阵列可以由厚氧化物FET构成，逻辑电路可以由同一芯片上的薄氧化物FET构成。 首先，在晶片上形成包括第一厚栅极SiO 2层的栅极堆叠。 堆叠包括在栅极氧化物层上的掺杂多晶硅层，多晶硅层上的硅化物层和硅化物层上的氮化物层。 选择性地去除堆叠的一部分以重新暴露将要形成逻辑电路的晶片。 在再曝光的晶片上形成更薄的栅氧化层。 接下来，在较薄的栅极氧化物层上形成栅极，并且在栅极处形成薄氧化物NFET和PFET。 在选择性硅化薄氧化物器件区域之后，在厚氧化物器件区域中从堆叠中蚀刻栅极。 最后，源极和漏极区域被注入并扩散用于厚栅极氧化物器件。

    Method of making a contact to a trench isolated device
    10.
    发明公开
    Method of making a contact to a trench isolated device 失效
    制造与TRENCH隔离装置接触的方法

    公开(公告)号：EP0238836A3

    公开(公告)日：1987-12-02

    申请号：EP87102194

    申请日：1987-02-17

    申请人： International Business Machines Corporation

    发明人： El-Kareh, Badih ,  Garnache, Richard Raymond ,  Ghatalia, Ashwin Kantilal

    IPC分类号： H01L21/31 ,  H01L21/76 ,  H01L27/10 ,  H01L21/312

    CPC分类号： H01L21/76237 ,  H01L21/743

    摘要： A method is provided for making a semiconductor structure which includes the steps of forming in a semiconductor body a P/N junction and a first opening (50, 54) in a first insulating layer (42) disposed on the surface of the semi­conductor body. A trench (22) is then formed in the semicon­ductor body having a sidewall located along a given plane through the opening and through the P/N junction. A second layer of insulation (56) is formed within the opening and on the sidewall of the trench. An insulating material (24) is disposed within the trench (22) and over the second insulat­ing layer (56) in the opening and a block (62) or segment of material is located over the trench (22) so as to extend a given distance from the trench over the upper surface of the body. The insulating material (24) and the block (62) are then etched so as to remove the block and the insulating material along the sides of the block. The exposed portions of the second insulating layer (56) are now etched to form a second opening therein within the first opening (50, 54) in the first insulating layer (42). A layer (64) of low viscosity material, such as a photoresist, is formed over the semicon­ductor body so as to cover the remaining portion of the insulating material (24), the layer (64) of low viscosity material and the insulating material (24) having similar etch rates. The layer (64) of low viscosity material and the insulating material (24) are then simultaneously etched directionally, e.g., by a reactive ion etching process (RIE), until all of the layer (64) of low viscosity material is removed to at least the surface of the second insulating layer (56) at the trench (22). Any suitable wet etchant may then be used, if desired, to remove any remaining low viscosity material disposed within the second opening in the second insulating layer. Metallic contacts (W T , W B , B O ) may now be formed, e.g., by evaporation, on the surface of the semiconductor body within the second opening in the second insulating layer without the concern that the metallic material will seep or enter into the trench causing a short at the P/N junction. In a preferred embodiment of the invention, the insulating material (24) is polyimide and the block (62) of material, as well as the layer (64) of low viscosity material, is made of photoresist.