公开(公告)号：EP0167764B1

公开(公告)日：1989-08-16

申请号：EP85106321.4

申请日：1985-05-23

申请人： International Business Machines Corporation

发明人： Lu, Nicky Chau-Chun ,  Ning, Tak Hung ,  Terman, Lewis Madison

IPC分类号： H01L27/10 ,  G11C11/24

CPC分类号： H01L27/10832 ,  H01L29/945

公开(公告)号：EP0068154B1

公开(公告)日：1989-03-08

申请号：EP82104709.9

申请日：1982-05-28

申请人： International Business Machines Corporation

发明人： Isaac, Randall Duane ,  Ning, Tak Hung ,  Yang, Denny Duan-Lee

IPC分类号： H01L21/76 ,  H01L21/74 ,  H01L23/52

CPC分类号： H01L21/76237 ,  H01L21/743 ,  H01L21/76202 ,  H01L23/535 ,  H01L29/0638 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP0021403A1

公开(公告)日：1981-01-07

申请号：EP80103559.3

申请日：1980-06-24

申请人： International Business Machines Corporation

发明人： Feth, George Clarence ,  Ning, Tak Hung ,  Tang, Denny Duan-Lee ,  Wiedmann, Siegfried Kurt ,  Yu, Hwa Nien

IPC分类号： H01L27/02 ,  H01L21/60 ,  H01L21/285 ,  H01L21/82

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L27/0233

摘要： Self-aligned semiconductor circuits and process for manufacturing the circuits in which a plurality of transistors (206, 208, 240; 206, 208, 242) is provided, the collector regions/contacts (240,228; 242, 228) and the base regions/contacts (254, 252; 256, 252) being mutually self-aligned. In one embodiment, the collectors have conductive layer contacts (such as metal) and are self-aligned to polysilicon base contacts while in another embodiment the base contacts are comprised of a conductive (metal) layer while polysilicon is used for the collector contacts. The collectors (240, 242) of these transistors can be butted to a recessed field oxide (214) to reduce the extrinsic base area and to minimize excess charge storage in the base region (208). The base contacts, whether polysilicon or metal, etc., provide alternate base current paths so that the removal of the extrinsic base area does not adversely affect the total amount of base current which can flow.

摘要翻译： 自对准半导体电路和制造其中提供多个晶体管（206,208,240; 206,208,242）的电路的工艺，集电极区域/触点（240,228; 242,228）和基极 区域/触点（254,252; 256,252）相互自对准。 在一个实施例中，集电器具有导电层接触（例如金属）并且与多晶硅基底触点自对准，而在另一实施例中，基极触点由导电（金属）层组成，而多晶硅用于集电极触点。 这些晶体管的集电极（240,242）可以对接到凹陷的场氧化物（214），以减少非本征基极面积并且使基极区域（208）中的过剩电荷存储最小化。 基极触点（无论多晶硅或金属等）是否提供可选的基极电流路径，以便去除非本征基极面积不会不利地影响可流过的基极电流的总量。

公开(公告)号：EP0167764A3

公开(公告)日：1986-03-05

申请号：EP85106321

申请日：1985-05-23

申请人： International Business Machines Corporation

发明人： Lu, Nicky Chau-Chun ,  Ning, Tak Hung ,  Terman, Lewis Madison

IPC分类号： H01L27/10 ,  G11C11/24

CPC分类号： H01L27/10832 ,  H01L29/945

摘要： A Dynamic Random Access Memory (DRAM) cell has a storage capacitor (3) disposed in a trench (5) formed in a semiconductor substrate (6). The substrate is heavily doped and forms the counterelectrode of the storage capacitor, and a heavily doped polycrystalline plug (4) disposed in the trench forms the other electrode. The DRAM cell includes an access transistor (8, 9, 10, 11) which is disposed adjacent the top of the storage capacitor, and source (8) of the access transistor is connected to the plug electrode (4).

公开(公告)号：EP0167764A2

公开(公告)日：1986-01-15

申请号：EP85106321.4

申请日：1985-05-23

申请人： International Business Machines Corporation

发明人： Lu, Nicky Chau-Chun ,  Ning, Tak Hung ,  Terman, Lewis Madison

IPC分类号： H01L27/10 ,  G11C11/24

CPC分类号： H01L27/10832 ,  H01L29/945

摘要： A Dynamic Random Access Memory (DRAM) cell has a storage capacitor (3) disposed in a trench (5) formed in a semiconductor substrate (6). The substrate is heavily doped and forms the counterelectrode of the storage capacitor, and a heavily doped polycrystalline plug (4) disposed in the trench forms the other electrode. The DRAM cell includes an access transistor (8, 9, 10, 11) which is disposed adjacent the top of the storage capacitor, and source (8) of the access transistor is connected to the plug electrode (4).

摘要翻译： 动态随机存取存储器（DRAM）单元具有设置在形成在半导体衬底（6）中的沟槽（5）中的存储电容器（3）。 衬底是重掺杂的并且形成存储电容器的反电极，并且设置在沟槽中的重掺杂多晶硅（4）形成另一个电极。 DRAM单元包括邻近存储电容器的顶部设置的存取晶体管（8,9,10,11），并且存取晶体管的源极（8）连接到插头电极（4）。

公开(公告)号：EP0096155A2

公开(公告)日：1983-12-21

申请号：EP83101750.4

申请日：1983-02-23

申请人： International Business Machines Corporation

发明人： Isaac, Randall Duane ,  Ning, Tak Hung

IPC分类号： H01L21/285 ,  H01L29/08

CPC分类号： H01L29/66272 ,  H01L21/28518 ,  H01L29/1004 ,  Y10S148/035

摘要： A vertical bipolar transistor structure has an extrinsic base region (4) covered by a metal silicide (eg WSi 2 ) layer (6) and a doped (eg with boron) polysilicon layer (7). The metal silicide and polysilicon layers (6, 7) have an opening therein with which the emitter (3) and intrinsic base region (2) of the transistor are aligned.
The vertical bipolar transistor structure can be produced by a method including delimiting a transistor area in a semiconductor substrate, depositing in succession over the the transistor area a silicide layer (6), a doped polysilicon layer (7) and a silicon dioxide layer (8), forming an aperture through the silicon dioxide, the doped polysilicon and the silicide layers, forming an insulating layer (8A) over the transistor area and driving in dopant from the polysilicon layer to form an extrinsic base region (4), removing the insulating layer from the base of the aperture but not from the sidewall of the aperture and forming an intrinsic base region and an emitter aligned with the aperture and the extrinsic base region.

摘要翻译： 一种垂直双极晶体管结构具有非本征基区（4）通过金属硅化物覆盖的（例如WSi2）层（6）和一个掺杂的（例如，用硼）的多晶硅层（7）。 金属硅化物层和多晶硅层（6,7）在开口在其中具有与该发射器（3）和本征基极区域（2）晶体管的排列。 ... 垂直双极晶体管结构可以通过包括在半导体衬底限定的晶体管区，陆续在该晶体管的区域上沉积的硅化物层的方法来制造（6），掺杂的多晶硅层（7）和一个 二氧化硅层（8）;形成在通过所述二氧化硅，掺杂的多晶硅和硅化物层孔，在晶体管区域的绝缘层（图8A）的形成和从多晶硅层中的掺杂剂驱动以在非本征基极区（4 ），从孔的底部而不是从所述孔的所述侧壁去除所述绝缘层和本征基极区和与所述孔和所述非本征基区对准发射极的形成。

公开(公告)号：EP0005721B1

公开(公告)日：1982-03-17

申请号：EP79101221.4

申请日：1979-04-23

申请人： International Business Machines Corporation

发明人： Ning, Tak Hung ,  Yu, Hwa Nien

IPC分类号： H01L21/60 ,  H01L23/48 ,  H01L21/285 ,  H01L29/54 ,  H01L29/62

CPC分类号： H01L21/033 ,  H01L21/2257 ,  H01L21/28525 ,  Y10S148/051 ,  Y10S148/124 ,  Y10S148/131

公开(公告)号：EP0721221A2

公开(公告)日：1996-07-10

申请号：EP95119364.8

申请日：1995-12-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ning, Tak Hung ,  Wu, Ben Song

IPC分类号： H01L29/423 ,  H01L29/732 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8228 ,  H01L21/8249

CPC分类号： H01L29/66265 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/78642

摘要： A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.

摘要翻译： 一种用于在绝缘体（SOI）技术中制造超大规模集成（ULSI）电路的工艺，其中可以是双极型，场效应晶体管或组合的器件结构形成在其下面和后面具有绝缘的垂直硅侧壁中 以便创建SKI设备结构。 当制造时，硅侧壁器件SOI结构采取单元的形式，每个单元具有多个双极器件，FET器件或这些器件的组合，诸如集电极，发射极，基极，源极，漏极和栅极 在单元中的器件的区域的平面内互连并且可以在相邻单元中的器件的区域的平面内互连。 此外，可以从硅侧壁的背面形成与相邻单元的互连。

公开(公告)号：EP0096155B1

公开(公告)日：1987-12-16

申请号：EP83101750.4

申请日：1983-02-23

申请人： International Business Machines Corporation

发明人： Isaac, Randall Duane ,  Ning, Tak Hung

IPC分类号： H01L21/285 ,  H01L29/08

CPC分类号： H01L29/66272 ,  H01L21/28518 ,  H01L29/1004 ,  Y10S148/035

公开(公告)号：EP0096155A3

公开(公告)日：1984-08-29

申请号：EP83101750

申请日：1983-02-23

申请人： International Business Machines Corporation

发明人： Isaac, Randall Duane ,  Ning, Tak Hung

IPC分类号： H01L21/285 ,  H01L29/08

CPC分类号： H01L29/66272 ,  H01L21/28518 ,  H01L29/1004 ,  Y10S148/035

摘要： A vertical bipolar transistor structure has an extrinsic base region (4) covered by a metal silicide (eg WSi 2 ) layer (6) and a doped (eg with boron) polysilicon layer (7). The metal silicide and polysilicon layers (6, 7) have an opening therein with which the emitter (3) and intrinsic base region (2) of the transistor are aligned. The vertical bipolar transistor structure can be produced by a method including delimiting a transistor area in a semiconductor substrate, depositing in succession over the the transistor area a silicide layer (6), a doped polysilicon layer (7) and a silicon dioxide layer (8), forming an aperture through the silicon dioxide, the doped polysilicon and the silicide layers, forming an insulating layer (8A) over the transistor area and driving in dopant from the polysilicon layer to form an extrinsic base region (4), removing the insulating layer from the base of the aperture but not from the sidewall of the aperture and forming an intrinsic base region and an emitter aligned with the aperture and the extrinsic base region.