公开(公告)号：EP3270411A1

公开(公告)日：2018-01-17

申请号：EP17189518.8

申请日：2016-06-20

申请人： IMEC vzw

发明人： DE WOLF, Ingrid ,  BOEMMELS, Juergen

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76825 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76877 ,  H01L23/53295 ,  H01L24/02 ,  H01L2224/02372

摘要： The present invention is related to a method for producing an integrated circuit device, comprising a Front-end-of-line (FEOL) portion and a Back-end-of-line (BEOL) portion. The metallization layers comprise dielectric layers, preferably low-k dielectric layers, with metal conductors and/or interconnect structures incorporated within said dielectric layers. In the method of the invention, a mask layer is applied on the BEOL stack or on one of the metallization layers during fabrication of the stack, said mask layer covering portions of the stack area and exposing other portions of said area. Then a treatment is performed that changes the elastic modulus of the dielectric material in one or more of the metallization layers, but only in the areas not covered by the mask layer.

摘要翻译： 本发明涉及一种用于制造集成电路器件的方法，所述集成电路器件包括前线工序（FEOL）部分和后工序后工序（BEOL）部分。 金属化层包括介电层，优选低k介电层，其中金属导体和/或互连结构结合在所述介电层内。 在本发明的方法中，在堆叠的制造期间在BEOL堆叠上或在其中一个金属化层上施加掩模层，所述掩模层覆盖部分堆叠区域并暴露所述区域的其他部分。 然后进行处理，其改变一个或多个金属化层中的电介质材料的弹性模量，但仅在未被掩模层覆盖的区域中。

公开(公告)号：EP4415035A1

公开(公告)日：2024-08-14

申请号：EP23155566.5

申请日：2023-02-08

申请人： Imec VZW

发明人： MIRABELLI, Gioele ,  BOEMMELS, Juergen ,  RYCKAERT, Julien

IPC分类号： H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/092 ,  H01L21/823871 ,  H01L21/823807 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/78696 ,  H01L27/0688 ,  H01L21/8221

摘要： This disclosure relates to complementary field effect transistor (CFET) devices, and is concerned with a routability of the transistor structures in a CFET cell. The disclosure presents a CFET cell (10) comprising a first transistor structure (11) in a first tier and a second transistor structure (12) in a second tier above the first tier. A first power rail (13) is arranged below the first tier and connected to the first transistor structure from below, and a second power rail (14) is formed in a first metal layer and connected to the second transistor structure from a first side. A set of signal routing lines (15) formed in a second metal layer above the second tier is connected to the first and second transistor structure from above. Further, a signal routing structure (16) formed in a metal zero (Mo) layer is connected to the first transistor structure and/or to the second transistor structure from a second side.

公开(公告)号：EP3961688A1

公开(公告)日：2022-03-02

申请号：EP20192545.0

申请日：2020-08-25

申请人： Imec VZW

发明人： CHAN, Boon Teik ,  BOEMMELS, Juergen ,  BRIGGS, Basoene

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8238

摘要： According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall (108), and the method comprising:
forming on a semiconductor layer of the substrate a first semiconductor layer stack (102) and a second semiconductor layer stack (104), each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer (114), wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; and
processing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks;
the method further comprising, prior to said processing:
by etching removing the sacrificial layer of each layer stack to form a respective cavity (122) on either sides of the insulating wall underneath the channel layer of the first and second layer stack, the channel layers being supported by the insulating wall; and
depositing a bottom insulating material (124) in said cavities;

wherein, subsequent to said processing, the bottom insulating material forms a bottom insulating layer underneath the source region, the drain region and the channel regions on either side of the insulating wall.

公开(公告)号：EP3840054A1

公开(公告)日：2021-06-23

申请号：EP19218708.6

申请日：2019-12-20

申请人： Imec VZW

发明人： DENTONI LITTA, Eugenio ,  BOEMMELS, Juergen ,  RYCKAERT, Julien ,  HORIGUCHI, Naoto ,  WECKX, Pieter

IPC分类号： H01L29/06 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/417 ,  H01L21/336 ,  H01L29/775

摘要： A method for forming a semiconductor device comprising forming a first transistor structure (10a) and a second transistor structure (20a) separated by a first trench which comprises a first dielectric wall (108) protruding above a top surface of the transistor structures. The first and the second transistor structures each comprise a plurality of stacked nanosheets (102a-b) forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further comprises depositing a contact material (136) over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion (120) of the first transistor structure and a first source/drain portion (124) of the second transistor structure. Further, the method comprises etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact (112a) contacting the first source/drain portion of the first transistor structure, and a second contact (112b) contacting the first source/drain portion of the second transistor structure.

公开(公告)号：EP3660890A1

公开(公告)日：2020-06-03

申请号：EP18208459.0

申请日：2018-11-27

申请人： IMEC vzw

发明人： LAZZARINO, Frederic ,  BOUCHE, Guillaume ,  BOEMMELS, Juergen

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/3213

摘要： According to an aspect of the present inventive concept there is provided a method for forming an interconnection structure for a semiconductor device, the method comprising:
forming a conductive layer on an insulating layer,
forming above the conductive layer a first set of mandrel lines of a first material,
forming a set of spacer lines of a second material different from the first material, wherein the spacer lines are formed on sidewalls of the first set of mandrel lines,
forming a second set of mandrel lines of a third material different from the first and second materials, wherein the second mandrel lines fill gaps between the spacer lines,
cutting at least a first mandrel line of the second set of mandrel lines into two line segments separated by a gap by etching said first mandrel line of the second set of mandrel lines selectively to the set of spacer lines and the first set of mandrel lines,
cutting at least a first mandrel line of the first set of mandrel lines into two line segments separated by a gap by etching said first mandrel line of the first set of mandrel lines selectively to the set of spacer lines and the second set of mandrel lines,
removing the set of spacer lines, selectively to the first and second sets of mandrel lines, thereby forming an alternating pattern of mandrel lines of the first set and mandrel lines of the second set, and
patterning the conductive layer to form a set of conductive lines, wherein the patterning comprises etching while using the alternating pattern of mandrel lines as an etch mask.

公开(公告)号：EP3599637A1

公开(公告)日：2020-01-29

申请号：EP18184958.9

申请日：2018-07-23

申请人： IMEC vzw

发明人： BRIGGS, Basoene ,  BOEMMELS, Juergen ,  WILSON, Christopher

IPC分类号： H01L23/522 ,  H01L21/768

摘要： According to an aspect of the present inventive concept there is provided a method for forming a multi-level interconnect structure on a substrate, the method comprising:
forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer,
forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer,
forming on the second interconnection level a third interconnection level, wherein forming the third interconnection level comprises:
forming a third dielectric layer,
forming a trench mask on the third dielectric layer, the trench mask comprising a pattern of trenches for defining positions of a third set of conductive structures to be formed in the third dielectric layer,
forming a multi-level via hole by etching the third dielectric layer in a region exposed within one of said trenches, said multi-level via hole extending through the third dielectric layer and the second dielectric layer to a structure of the first set of conductive structures such that a surface of said structure is exposed at a bottom of the multi-level via hole,
selectively depositing a first conductive material in the multi-level via hole on said structure of the first set of conductive structures,
transferring the pattern of the trench mask into the third dielectric layer by etching to form a set of dielectric layer trenches for accommodating the third set of conductive structures, and
depositing a second conductive material filling said set of dielectric layer trenches, wherein the second conductive material deposited in one of the dielectric layer trenches is deposited on said first conductive material selectively deposited in the multi-level via hole.

公开(公告)号：EP3581543A1

公开(公告)日：2019-12-18

申请号：EP18178065.1

申请日：2018-06-15

申请人： IMEC vzw

发明人： WECKX, Pieter ,  BOEMMELS, Juergen ,  RYCKAERT, Julien

IPC分类号： B82Y10/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L27/04 ,  H01L29/78 ,  H01L29/06 ,  H01L27/06 ,  H01L27/11

摘要： According to an inventive aspect there is provided a semiconductor device comprising:
first and second sets of transistors (100, 200) comprising a pass transistor (110, 210) and a stacked complementary transistor pair (120, 220) of a lower transistor (122, 222) and an upper transistor (124, 224),
wherein first transistor comprises a semiconductor channel (110c, 122c, 124c) extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a separate second fin track parallel to the first fin track, and
wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level,
a first tall gate electrode (130) forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and
a first short gate electrode (140) forming a gate for the first pass transistor and arranged along a second gate track,
a second tall gate electrode (230) forming a common gate for the second complementary transistor pair and arranged along the second gate track,
a second short gate electrode (240) forming a gate for the second pass transistor and arranged along the first gate track,
first and second contact arrangements (150, 250) forming a common drain contact for the transistors of the first set and the second set, respectively, and
first and second cross-couple contacts (170, 270) extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively.

公开(公告)号：EP3439031A1

公开(公告)日：2019-02-06

申请号：EP17184398.0

申请日：2017-08-02

申请人： IMEC vzw

发明人： BOEMMELS, Juergen ,  DEBACKER, Peter ,  GUPTA, Anshul

IPC分类号： H01L23/528 ,  H01L23/522

摘要： According to an aspect of the present inventive concept there is provided a method for forming a multi-level interconnect structure for a semiconductor device, the method comprising:
forming a first interconnection level including a set of conductive lines arranged in a first common horizontal plane of the first interconnection level and extending parallel to a first direction,
forming a second interconnection level, wherein forming the second interconnection level comprises:
forming, on the first interconnection level, a first sub-level of the second interconnection level, the first sub-level including a set of conductive lines arranged in a first common horizontal plane of the second interconnection level and extending parallel to a second direction transverse to the first direction, and
forming, on the first sub-level of the second interconnection level, a second sub-level of the second interconnection level, the second sub-level including a set of conductive lines arranged in a second common horizontal plane of the second interconnection level and extending parallel to the second direction,
wherein the first and the second sub-levels of the second interconnection level are formed as consecutive sub-levels and wherein said set of lines of the first sub-level of the second interconnection level and said set of lines of the second sub-level of the second interconnection level are horizontally displaced in relation to each other, and

forming a vertical via for interconnecting a line of said set of lines of the first interconnection level and a line of said set of lines of the second sub-level of the second interconnection level, wherein the via extends past said set of lines of the first sub-level of the second interconnection level in a space between a pair of adjacent lines of said set of lines of the first sub-level of the second interconnection level.

公开(公告)号：EP3404707A1

公开(公告)日：2018-11-21

申请号：EP17171135.1

申请日：2017-05-15

申请人： IMEC vzw

发明人： BOEMMELS, Juergen

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L27/11

CPC分类号： H01L29/7827 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/1104 ,  H01L29/152 ,  H01L29/66666

摘要： According to an aspect of the present inventive concept there is provided a method for forming interconnected vertical channel devices on a semiconductor structure comprising a first vertical channel structure (111) extending from a first bottom electrode region and a second vertical channel structure (112) extending from a second bottom electrode region, the first and the second vertical channel structures protruding from a dielectric layer (108) covering the first and second bottom electrode regions, the method comprising:
forming a first hole exposing the first bottom electrode region and a second hole exposing the second bottom electrode region, the first and the second hole extending vertically through the dielectric layer, and
forming a conductive pattern (130') including a set of discrete pattern parts (132, 134) on the dielectric layer, wherein forming the conductive pattern includes:
forming a first pattern part (132) including a first gate portion (132g) wrapping around a protruding portion of the first vertical channel structure (111), a first bottom electrode contact portion (132b) arranged in the second hole, and a first cross-coupling portion (132x) extending between the first bottom electrode contact portion (132b) and the first gate portion (132g), and
forming a second pattern part (134) including a second gate portion (134g) wrapping around a protruding portion of the second vertical channel structure (112), a second bottom electrode contact portion (134b) arranged in the first hole, and a cross-coupling portion (134x) extending between the second bottom electrode contact portion (134b) and the second gate portion (132g).

公开(公告)号：EP4199113A1

公开(公告)日：2023-06-21

申请号：EP21215814.1

申请日：2021-12-20

申请人： IMEC VZW

发明人： BRIGGS, Basoene ,  CHAN, Boon Teik ,  BOEMMELS, Juergen

IPC分类号： H01L29/775 ,  H01L21/336 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  B82Y10/00

摘要： According to an aspect there is provided a method for forming a semiconductor device structure, the method comprising:
forming a layer stack on a substrate, the layer stack comprising sacrificial layers of a first semiconductor material and channel layers of a second semiconductor material, the channel layers alternating the sacrificial layers;
forming over the layer stack a plurality of parallel and regularly spaced core lines;
forming spacer lines on side surfaces of the core lines, wherein a width of the spacer lines is such that gaps are formed between spacer lines formed on neighboring core lines;
forming first trenches extending through the layer stack by etching the layer stack while using the core lines and the spacer lines as an etch mask;
forming insulating walls in the first trenches and in the gaps by filling the first trenches and the gaps with insulating wall material;
subsequent to forming the insulating walls, removing the core lines selectively to the spacer lines and the insulating walls; and
subsequent to removing the core lines, forming second trenches extending through the layer stack by etching the layer stack while using the spacer lines and the insulating walls as an etch mask, thereby forming a plurality of pairs of fin structures, each pair of fin structures comprising a first device layer stack and a second device layer stack separated by a respective insulating wall.