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    SEMICONDUCTOR PACKAGE WITH FUNCTIONALLY REDUNDANT SEMICONDUCTOR DIES
    4.
    发明公开
    SEMICONDUCTOR PACKAGE WITH FUNCTIONALLY REDUNDANT SEMICONDUCTOR DIES 审中-公开

    公开(公告)号：EP3514829A1

    公开(公告)日：2019-07-24

    申请号：EP18209347.6

    申请日：2018-11-29

    申请人： INTEL Corporation

    发明人： GOMES, Wilfred ,  BOHR, Mark T. ,  SHEREL, Udi ,  NEIBERG, Leonard M. ,  NASSIF, Nevine ,  MC CULLOUGH, Wesley D.

    IPC分类号： H01L25/065 ,  H04L12/40 ,  H01L25/18

    摘要： Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.

    VIA BLOCKING LAYER
    8.
    发明公开
    VIA BLOCKING LAYER 审中-公开
    威盛阻塞层

    公开(公告)号：EP3238236A1

    公开(公告)日：2017-11-01

    申请号：EP14909245.4

    申请日：2014-12-23

    申请人： Intel Corporation

    发明人： HOURANI, Rami ,  KRYSAK, Marie ,  GSTREIN, Florian ,  BRAIN, Ruth A. ,  BOHR, Mark T.

    IPC分类号： H01L21/3205 ,  H01L21/28

    CPC分类号： H01L21/76807 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/528 ,  H01L2221/1031 ,  H01L2221/1063

    摘要： Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

    摘要翻译： 公开了用于绝缘或电隔离给定互连层内的选择通孔的技术，因此导电路由可跳过那些选择隔离通孔以到达同一层中的其他通孔或互连。 根据需要，这种通孔阻挡层可以选择性地在给定互连内的任意数量的位置中实现。 还提供了用于形成通孔阻挡层的技术，包括使用牺牲钝化层来促进形成通孔阻挡层的绝缘体材料的选择性沉积的第一方法，使用湿 - 可渗透聚合物制剂的旋涂的第二方法， 促进形成通孔阻挡层的绝缘体材料的选择性沉积，以及第三种方法，其使用纳米粒子制剂的旋涂来促进选择性沉积形成通孔阻挡层的绝缘体材料。 避免了通常与保形沉积工艺相关的有害蚀刻工艺。

    VIA BLOCKING LAYER
    10.
    发明公开
    VIA BLOCKING LAYER 审中-公开

    公开(公告)号：EP3955280A1

    公开(公告)日：2022-02-16

    申请号：EP21198959.5

    申请日：2014-12-23

    申请人： INTEL Corporation

    发明人： HOURANI, Rami ,  KRYSAK, Marie ,  GSTREIN, Florian ,  BRAIN, Ruth A. ,  BOHR, Mark T.

    IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/522

    摘要： Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.