公开(公告)号：EP1490454B1

公开(公告)日：2012-08-15

申请号：EP03731976.1

申请日：2003-01-17

申请人： Silecs OY

发明人： RANTALA, Juha ,  REID, Jason ,  TORMANEN, Teemu ,  VISWANATHAN, Nungavaram, Sundaram ,  MAANINEN, Arto, L., T.

IPC分类号： H01L21/312 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/3122 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/316 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5329 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： An integrated circuit is provided comprising a substrate and discrete areas of electrically insulating and electrically conductive material, wherein the electrically insulating material is a hybrid organic-inorganic material that has a density of 1.45 g/cm3 or more and a dielectric constant of 30.0 or less. The integrated circuit can be made by a method comprising: providing a substrate; forming discrete areas of electrically insulating and electrically conductive material on the substrate; wherein the electricaly insulating material is deposited on the substrate followed by heating at a temperature of 350 °C or less; and whrein the electrically insulating material is a hybrid organic-inorganic material that has a density of 1.45 g/cm3 or more after densification. Also disclosed is a method for making an integrated circuit comprising performing a dual damascene method with an electrically conductive material and a dielectric, the dielectric being a directly photopatterned hybrid organic-inorganic material. A method for making an integrated circuit is disclosed as comprising depositing alternating regions of electrically conductive and dielectric materials on a substrate, wherein an area of dielectric material is formed by: a silane precursor having a fully or partially fluorinated first organic group comprising an unsaturated carbon-carbon double bond, the fully or partially fluorinated organic group bound to silicon in the silane precursor; forming from the silane precursor a hybrid organic-inorganic material having a molecular weight of at least 500 on a substrate; and increasing the molecular weight of the hybrid by crosslinking via the fully or partially fluorinated orgnanic group.

公开(公告)号：EP0373344A3

公开(公告)日：1991-04-24

申请号：EP89120347.3

申请日：1989-11-03

申请人： International Business Machines Corporation

发明人： Cronin, John Edward ,  Kaanta, Carter Welling ,  Leach, Michael Albert

IPC分类号： H01L21/90

CPC分类号： H01L21/76808 ,  H01L21/32053 ,  H01L21/4846 ,  H01L21/76877 ,  H01L21/7688 ,  H01L2221/1031 ,  H01L2221/1036 ,  H05K3/0017 ,  H05K3/06 ,  H05K3/107 ,  H05K3/4644 ,  Y10T29/49158

摘要： A method for forming an electrically conductive line between two layers of insulating material and method for connecting the line through both layers of the insulating material to the opposite surfaces is provided. In the method, first, second and third layers (10, 20, 28) of insulating material are provided wherein said first and third layers are separated by said second layer of insulating material which is different in etch rate from the first and third layers. The edge portion of all three layers is exposed and the insulating layer of the second material is selectively etched to remove the revealed edge portion and provide a slot (36) between the first (10) and third (28) layers of insulating material. Also openings (38) are provided in both the first and third layers of insulating material which communicate with the slot and extend respectively through the layers of the first and third insulating material. Thereafter, a conductive material such as tungsten is deposited in the slot and the openings and also on the face of the stacked insulating material. Finally, the excess tungsten is removed from the faces of the insulating material of the first and third layers leaving a conductive line sandwiched between the first and third insulating layers of the material; also metal remains in the openings formed to thereby form conductive studs extending from the line to the opposite surfaces of the insulating material sandwich so formed.

公开(公告)号：EP1120822A4

公开(公告)日：2004-11-10

申请号：EP99940607

申请日：1999-09-01

申请人： TOKYO ELECTRON LTD

发明人： AKAHORI TAKASHI ,  INAZAWA KOUICHIRO ,  SENOO KOUJI ,  HAGIWARA MASAAKI

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768

CPC分类号： H01L21/76832 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/3127 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76835 ,  H01L2221/1031 ,  H01L2221/1036

摘要： A semiconductor device using, e.g., a fluorine containing carbon film, as an interlayer dielectric film is produced by a dual damascene method which is a simple technique. After an dielectric film, e.g., an SiO2 film 3, is deposited on a substrate 2, the SiO2 film 3 is etched to form a via hole 31 therein, and then, a top dielectric film, e.g., a CF film 4, is deposited on the top face of the SiO2 film 3. If the CF film is deposited by activating a thin-film deposition material having a bad embedded material, e.g., C6F6 gas, as a plasma, the CF film 4 can be deposited on the top face of the SiO2 film 3 while inhibiting the CF film from being embedded into the via hole 31. Subsequently, by etching the CF film 4 to form a groove 41 therein, it is possible to easily produce a dual damascene shape wherein the groove 41 is integrated with the via hole 31.

公开(公告)号：EP0373344A2

公开(公告)日：1990-06-20

申请号：EP89120347.3

申请日：1989-11-03

申请人： International Business Machines Corporation

发明人： Cronin, John Edward ,  Kaanta, Carter Welling ,  Leach, Michael Albert

IPC分类号： H01L21/90

CPC分类号： H01L21/76808 ,  H01L21/32053 ,  H01L21/4846 ,  H01L21/76877 ,  H01L21/7688 ,  H01L2221/1031 ,  H01L2221/1036 ,  H05K3/0017 ,  H05K3/06 ,  H05K3/107 ,  H05K3/4644 ,  Y10T29/49158

摘要： A method for forming an electrically conductive line between two layers of insulating material and method for connecting the line through both layers of the insulating material to the opposite surfaces is provided. In the method, first, second and third layers (10, 20, 28) of insulating material are provided wherein said first and third layers are separated by said second layer of insulating material which is different in etch rate from the first and third layers. The edge portion of all three layers is exposed and the insulating layer of the second material is selectively etched to remove the revealed edge portion and provide a slot (36) between the first (10) and third (28) layers of insulating material. Also openings (38) are provided in both the first and third layers of insulating material which communicate with the slot and extend respectively through the layers of the first and third insulating material. Thereafter, a conductive material such as tungsten is deposited in the slot and the openings and also on the face of the stacked insulating material. Finally, the excess tungsten is removed from the faces of the insulating material of the first and third layers leaving a conductive line sandwiched between the first and third insulating layers of the material; also metal remains in the openings formed to thereby form conductive studs extending from the line to the opposite surfaces of the insulating material sandwich so formed.

摘要翻译： 提供了一种用于在绝缘材料和方法，用于绝缘材料的两个层连接到删除线的相对表面的两个层之间的导电线形成方法。 在绝缘材料制成，第一，第二和第三层（10，20，28）的方法被提供worin所述第一和第三层是由绝缘材料制成的所有这是在从所述第一层和第三层的蚀刻速率不同的所述第二层分离。 所有三个层的边缘部分被暴露，所述第二材料构成的绝缘层被选择性地蚀刻，以除去揭示边缘部分和提供第一（10）之间的槽（36）和绝缘材料的第三（28）层。 所以在与该槽相通并分别通过第一和第三绝缘材料的开口（38）的层延伸的绝缘材料。第一层和第三层提供。 有后，导电材料：诸如钨在插槽和开口等层叠的绝缘材料的表面沉积。 最后，将过量的钨从第一层和第三层在离开夹在材料的第一和第三绝缘层之间的导电线的绝缘材料的面除去 所以金属残留在形成为从而开口形成导电柱从线到如此形成的绝缘材料夹层结构的相对的表面延伸。

公开(公告)号：EP0259370A1

公开(公告)日：1988-03-16

申请号：EP87901067.0

申请日：1987-01-28

申请人： PLESSEY OVERSEAS LIMITED

发明人： WILLIAMS, Brian, David

IPC分类号： H01L21

CPC分类号： H01L21/76808 ,  H01L21/7684 ,  H01L21/76877 ,  H01L2221/1031

摘要： Le procédé de production ci-décrit se rapporte à des pistes d'interconnexions métalliques dont l'épaisseur est égale ou supérieure à la moitié de leur largeur, afin d'obtenir un espacement plus étroit entre les composants du circuit intégré et, partant, une meilleure utilisation de l'espace entre les surfaces des semi-conducteurs. Ledit procédé (fig. 3) utilise la dépôt d'un film diélectrique (7) relativement fin (2 mum) et la délinéation dudit film (7) à l'aide d'un masque résistant à la corrosion (9) ainsi qu'une technique d'attaque anisotropique permettant de définir des canaux profonds d'une largeur inférieure ou égale à deux microns devant contenir le métal d'interconnexion. Le métal (13) est déposé par une technique analogue permettant de remplir les canaux et de retirer ensuite le métal excédentaire, afin de définir une structure d'interconnexion, formée des pistes métalliques (15). Dans un mode de réalisation décrit, le matériau diélectrique de polyimides est attaqué par du plasma d'oxygène à l'aide d'un masque de tungstène, le métal de tungstène formant l'interconnexion étant déposé par dépôt en phase gazeuse par procédé chimique à base pression. Dans une variante, un matériau diélectrique au bioxyde de silicium et des masques d'aluminium ainsi qu'un matériau de métallisation peuvent être utilisés avec des décapants appropriés.

公开(公告)号：EP3238236A1

公开(公告)日：2017-11-01

申请号：EP14909245.4

申请日：2014-12-23

申请人： Intel Corporation

发明人： HOURANI, Rami ,  KRYSAK, Marie ,  GSTREIN, Florian ,  BRAIN, Ruth A. ,  BOHR, Mark T.

IPC分类号： H01L21/3205 ,  H01L21/28

CPC分类号： H01L21/76807 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/528 ,  H01L2221/1031 ,  H01L2221/1063

摘要： Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

摘要翻译： 公开了用于绝缘或电隔离给定互连层内的选择通孔的技术，因此导电路由可跳过那些选择隔离通孔以到达同一层中的其他通孔或互连。 根据需要，这种通孔阻挡层可以选择性地在给定互连内的任意数量的位置中实现。 还提供了用于形成通孔阻挡层的技术，包括使用牺牲钝化层来促进形成通孔阻挡层的绝缘体材料的选择性沉积的第一方法，使用湿 - 可渗透聚合物制剂的旋涂的第二方法， 促进形成通孔阻挡层的绝缘体材料的选择性沉积，以及第三种方法，其使用纳米粒子制剂的旋涂来促进选择性沉积形成通孔阻挡层的绝缘体材料。 避免了通常与保形沉积工艺相关的有害蚀刻工艺。

公开(公告)号：EP1607493A3

公开(公告)日：2007-07-04

申请号：EP05014450.0

申请日：1999-02-10

申请人： APPLIED MATERIALS, INC.

发明人： Cheung, David ,  Yau, Wai-Fan ,  Mandal, Robert P. ,  Jeng, Shin-Puu ,  Liu, Kuo-Wei ,  Lu, Yung-Cheng ,  Barnes, Mike ,  Willecke, Ralf B. ,  Moghadam, Farhad ,  Ishikawa, Tetsuya ,  Poon, Tze

IPC分类号： H01L21/316 ,  C23C16/40 ,  H01L21/768

CPC分类号： H01L21/76835 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2221/1031

摘要： A method for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas at a constant RF power level from about 10W to about 200W or a pulsed RF power level from about 20W to about 500W. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organosilane film is produced by reaction of methylsilane, CH 3 SIH 3 , dimethylsilane, (CH 3 ) 2 SiH 2 , or 1,1,3,3-tetramethyldisiloxane, (CH 3 ) 2 -SiH-O-SiH-(CH 3 ) 2 , and nitrous oxide, N 2 O, at a constant RF power level from about 10W to about 150W, or a pulsed RF power level from about 20W to about 250W during 10 % to 30% of the duty cycle.

摘要翻译： 一种通过有机硅化合物和氧化气体以约10W至约200W的恒定RF功率水平的反应沉积低介电常数膜的方法或约20W至约500W的脉冲RF功率水平的方法。 在与有机硅化合物混合之前，优选在单独的微波室内可以提高氧化气体的离解，以有助于控制沉积膜的碳含量。 氧化的有机硅烷或有机硅氧烷膜具有良好的屏障性能，用作邻近其它电介质层的衬垫或盖层。 氧化的有机硅烷或有机硅氧烷膜也可以用作蚀刻停止层和用于制造双镶嵌结构的金属间介电层。 氧化的有机硅烷或有机硅氧烷膜也提供不同介电层之间优异的粘附性。 优选的氧化有机硅烷膜是通过甲基硅烷，CH 3 SIH 3，二甲基硅烷，（CH 3）2 SiH 2或1,1,3,3-四甲基二硅氧烷，（CH 3）2 -SiH-O-SiH- （CH 3）2和一氧化二氮N 2 O，在约10W至约150W的恒定RF功率水平下，或在占空比的10％至30％期间的约20W至约250W的脉冲RF功率水平。

公开(公告)号：EP1120822A1

公开(公告)日：2001-08-01

申请号：EP99940607.7

申请日：1999-09-01

申请人： TOKYO ELECTRON LIMITED

发明人： AKAHORI, Takashi ,  INAZAWA, Kouichiro ,  SENOO, Kouji ,  HAGIWARA, Masaaki

IPC分类号： H01L21/3205 ,  H01L21/768

CPC分类号： H01L21/76832 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/3127 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76835 ,  H01L2221/1031 ,  H01L2221/1036

摘要： A semiconductor device using, e.g., a fluorine containing carbon film, as an interlayer dielectric film is produced by a dual damascene method which is a simple technique.
After an dielectric film, e.g., an SiO 2 film 3, is deposited on a substrate 2, the SiO 2 film 3 is etched to form a via hole 31 therein, and then, a top dielectric film, e.g., a CF film 4, is deposited on the top face of the SiO 2 film 3. If the CF film is deposited by activating a thin-film deposition material having a bad embedded material, e.g., C 6 F 6 gas, as a plasma, the CF film 4 can be deposited on the top face of the SiO2 film 3 while inhibiting the CF film from being embedded into the via hole 31. Subsequently, by etching the CF film 4 to form a groove 41 therein, it is possible to easily produce a dual damascene shape wherein the groove 41 is integrated with the via hole 31.

摘要翻译： 使用例如含氟碳膜作为层间绝缘膜的半导体器件通过双镶嵌法制造，这是一种简单的技术。 在基板2上沉积例如SiO2膜3的电介质膜之后，蚀刻SiO 2膜3以在其中形成通孔31，然后沉积顶部电介质膜例如CF膜4 在SiO 2膜3的顶面上。如果通过激活作为等离子体的具有不良嵌入材料（例如C 6 F 6气体）的薄膜沉积材料来沉积CF膜，则可以将CF膜4沉积在顶表面 同时抑制CF膜被嵌入到通孔31中。随后，通过蚀刻CF膜4以在其中形成凹槽41，可以容易地产生双镶嵌形状，其中凹槽41被集成 与通孔31.

公开(公告)号：EP0834916A3

公开(公告)日：1998-07-29

申请号：EP97116851.3

申请日：1997-09-29

申请人： MOTOROLA, INC.

发明人： Boeck, Bruce Allen ,  Wetzel, Jeff Thomas ,  Sparks, Terry Grant

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76885 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure having a dielectric layer with low dielectric constant is formed within an integrated circuit. In one embodiment of the invention, portions of a silicon dioxide layer (18) lying adjacent to a conductive interconnect (21) are removed to expose portions of a silicon nitride etch stop layer (16). A dielectric layer (22) having a low dielectric constant is then formed overlying the conductive interconnect (21) and the exposed portions of the silicon nitride etch stop layer (16). A portion of the dielectric layer (22) is then removed to expose the top surface of the conductive interconnect (21) to leave portions of the dielectric layer (22) between adjacent conductive interconnects (21). The resulting interconnect structure has reduced cross-talk between conductive interconnects (21) while avoiding prior art disadvantages of reduced thermal dissipation and increased mechanical stress.

公开(公告)号：EP0557278A1

公开(公告)日：1993-09-01

申请号：EP91904608.0

申请日：1991-02-01

申请人： International Business Machines Corporation

发明人： CHANG, Kenneth ,  CZORNYJ, George ,  FAROOQ, Mukta, Shaji ,  KUMAR, Ananda, Hosakere ,  STEIMEL, Heinz, Otto

IPC分类号： H01L23 ,  H01L21 ,  H05K3

CPC分类号： H01L21/76808 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/76807 ,  H01L2221/1031 ,  H01L2221/1036 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/184 ,  H05K3/388 ,  H05K3/465 ,  H05K3/4661 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/107

摘要： Procédé de fabrication d'une structure de film mince multicouche sur la surface d'un substrat diélectrique, ledit procédé comprenant les étapes suivantes: a) la formation d'une structure de film mince multicouche comme suit: (i) en appliquant une première couche de matériau polymère diélectrique sur la surface d'un substrat diélectrique, (ii) en appliquant une deuxième couche de matériau polymère diélectrique sur la première couche de matériau polymère diélectrique, le deuxième matériau polymère étant photosensible, (iii) en exposant et en développant comme une image le deuxième matériau polymère pour y former un motif, le motif de la deuxième couche étant relié à au moins un motif formé dans le premier matériau polymère; et b) le remplissage des motifs dans la totalité de la structure multicouche avec un matériau conducteur. De préférence, le motif de la première couche est une voie de passage et le motif de la deuxième couche est un réseau atténuateur d'étouffement ou une gouttière d'interconnexion. L'invention concerne également une structure de film mince multicouche fabriquée selon ce procédé.