公开(公告)号：EP3559983A1

公开(公告)日：2019-10-30

申请号：EP16924501.6

申请日：2016-12-23

Applicant: INTEL Corporation

Inventor： GSTREIN, Florian ,  HAN, Eungnak ,  HOURANI, Rami ,  BRAIN, Ruth A. ,  NYHUS, Paul A. ,  CHANDHOK, Manish ,  WALLACE, Charles H. ,  TSANG, Chi-Hwa

IPC: H01L21/768

公开(公告)号：EP3314643A1

公开(公告)日：2018-05-02

申请号：EP15896579.8

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： LIN, Kevin ,  BRISTOL, Robert Lindsey ,  BLACKWELL, James M. ,  HOURANI, Rami

IPC: H01L21/768 ,  H01L21/31

CPC classification number: H01L23/5226 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53209 ,  H01L23/53295

Abstract: Embodiments of the invention include an interconnect structure with a via and methods of forming such structures. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD). A first interconnect line and a second interconnect line extend into the first ILD. According to an embodiment, a second ILD is positioned over the first interconnect line and the second interconnect line. A via may extend through the second ILD and electrically coupled to the first interconnect line. Additionally, embodiments of the invention include a portion of a bottom surface of the via being positioned over the second interconnect line. However, an isolation layer may be positioned between the bottom surface of the via and a top surface of the second interconnect line, according to an embodiment of the invention.

公开(公告)号：EP3238236A1

公开(公告)日：2017-11-01

申请号：EP14909245.4

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： HOURANI, Rami ,  KRYSAK, Marie ,  GSTREIN, Florian ,  BRAIN, Ruth A. ,  BOHR, Mark T.

IPC: H01L21/3205 ,  H01L21/28

CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/528 ,  H01L2221/1031 ,  H01L2221/1063

Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

Abstract translation: 公开了用于绝缘或电隔离给定互连层内的选择通孔的技术，因此导电路由可跳过那些选择隔离通孔以到达同一层中的其他通孔或互连。 根据需要，这种通孔阻挡层可以选择性地在给定互连内的任意数量的位置中实现。 还提供了用于形成通孔阻挡层的技术，包括使用牺牲钝化层来促进形成通孔阻挡层的绝缘体材料的选择性沉积的第一方法，使用湿 - 可渗透聚合物制剂的旋涂的第二方法， 促进形成通孔阻挡层的绝缘体材料的选择性沉积，以及第三种方法，其使用纳米粒子制剂的旋涂来促进选择性沉积形成通孔阻挡层的绝缘体材料。 避免了通常与保形沉积工艺相关的有害蚀刻工艺。

公开(公告)号：EP3198652A1

公开(公告)日：2017-08-02

申请号：EP14902843.3

申请日：2014-09-26

Applicant: INTEL Corporation

Inventor： CLENDENNING, Scott B. ,  LIAO, Szuya S. ,  GSTREIN, Florian ,  HOURANI, Rami ,  ROMERO, Patricio E. ,  KLOSTER, Grant M. ,  MITAN, Martin M.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0673 ,  H01L21/265 ,  H01L21/28247 ,  H01L29/42364 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

Abstract translation: 讨论了与用于形成用于半导体器件的选择性栅极隔离物和使用这种技术形成的晶体管结构和器件有关的技术。 这种技术包括在半导体鳍片上形成阻挡材料，在阻挡材料的一部分上设置具有与阻挡材料不同表面化学性质的栅极，在栅极上而不是在阻挡材料的一部分上形成选择性共形层， 并去除阻挡材料的暴露部分。

公开(公告)号：EP3475973A1

公开(公告)日：2019-05-01

申请号：EP16906441.7

申请日：2016-06-22

Applicant: INTEL Corporation

Inventor： HOURANI, Rami ,  KRYSAK, Marie ,  GSTREIN, Florian ,  BRAIN, Ruth A. ,  BOHR, Mark T. ,  CHANDHOK, Manish

IPC: H01L21/768 ,  H01L21/02

公开(公告)号：EP3311403A1

公开(公告)日：2018-04-25

申请号：EP15895813.2

申请日：2015-06-18

Applicant: Intel Corporation

Inventor： CLENDENNING, Scott B. ,  MITAN, Martin M. ,  GLASSMAN, Timothy E. ,  GRIGGIO, Flavio ,  KLOSTER, Grant M. ,  FRASURE, Kent N. ,  GSTREIN, Florian ,  HOURANI, Rami

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/76879 ,  C23C16/045 ,  H01L21/28 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76865 ,  H01L21/76876 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2221/1063

Abstract: Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.

公开(公告)号：EP3289608A1

公开(公告)日：2018-03-07

申请号：EP15890917.6

申请日：2015-04-29

Applicant: Intel Corporation

Inventor： CHAWLA, Jasmeet S. ,  HOURANI, Rami ,  KOBRINSKY, Mauro J. ,  GSTREIN, Florian ,  CLENDENNING, Scott B. ,  ROBERTS, Jeanette M.

IPC: H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2221/101 ,  H01L2221/1063

Abstract: A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.

公开(公告)号：EP3050084A1

公开(公告)日：2016-08-03

申请号：EP13894765.0

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： BRISTOL, Robert L. ,  BLACKWELL, James M. ,  CLENDENNING, Scott B. ,  GSTREIN, Florian ,  HAN, Eungnak ,  KLOSTER, Grant M. ,  ROBERTS, Jeanette M. ,  ROMERO, Patricio E. ,  HOURANI, Rami

IPC: H01L21/31

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

公开(公告)号：EP3955280A1

公开(公告)日：2022-02-16

申请号：EP21198959.5

申请日：2014-12-23

Applicant: INTEL Corporation

Inventor： HOURANI, Rami ,  KRYSAK, Marie ,  GSTREIN, Florian ,  BRAIN, Ruth A. ,  BOHR, Mark T.

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

公开(公告)号：EP3796394A1

公开(公告)日：2021-03-24

申请号：EP20181036.3

申请日：2020-06-19

Applicant: INTEL Corporation

Inventor： METZ, Matthew ,  GSTREIN, Florian ,  MITAN, Martin ,  HOURANI, Rami ,  CLENDENNING, Scott ,  LIAO, Szuya ,  TORRES, Jessica ,  CHIKKADI, Kiran ,  BAUMGARTEL, Lukas ,  LANCASTER, Diane

IPC: H01L29/66 ,  H01L29/78

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.