公开(公告)号：EP3050113A1

公开(公告)日：2016-08-03

申请号：EP13894617.3

申请日：2013-09-27

申请人： Intel Corporation

发明人： RACHMADY, Willy ,  LE, Van H. ,  PILLARISETTY, Ravi ,  RADOSAVLJEVIC, Marko ,  DEWEY, Gilbert ,  MUKHERJEE, Niloy ,  KAVALIEROS, Jack T. ,  CHAU, Robert S. ,  CHU-KUNG, Benjamin ,  KOTLYAR, Roza

IPC分类号： H01L29/78 ,  H01L29/20 ,  H01L21/336

CPC分类号： H01L29/7842 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/512 ,  H01L29/66439 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696

摘要： An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first band gap less than a band gap of a material of the substrate and a second material having a second band gap that is greater than the first band gap; and a gate stack on the channel region, wherein the second material is disposed between the first material and the gate stack. A method including forming a first material having a first band gap on a substrate; forming a second material having a second band gap greater than the first band gap on the first material; and forming a gate stack on the second material.

公开(公告)号：EP2656392A2

公开(公告)日：2013-10-30

申请号：EP11851579.0

申请日：2011-12-07

申请人： Intel Corporation

发明人： MURTHY, Anand S. ,  GLASS, Glenn A. ,  GHANI, Tahir ,  PILLARISETTY, Ravi ,  MUKHERJEE, Niloy ,  KAVALIEROS, Jack T. ,  KOTLYAR, Roza ,  RACHMADY, Willy ,  LIU, Mark Y.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in Sight of this disclosure, including both planar and non-planar transistor structures {e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type de vices, but can be used for n-type de vices if so desired.

公开(公告)号：EP3127162A1

公开(公告)日：2017-02-08

申请号：EP14886770.8

申请日：2014-03-27

申请人： Intel Corporation

发明人： PILLARISETTY, Ravi ,  LE, Van ,  RACHMADY, Willy ,  KOTLYAR, Roza ,  RADOSVLJEVIC, Marko ,  THEN, Han Wui ,  DASGUPTA, Sansaptak ,  DEWEY, Gilbert ,  CHU-KUNG, Benjamin ,  KAVALIEROS, Jack

IPC分类号： H01L29/78 ,  H01L27/11

CPC分类号： H01L29/161 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： Techniques related to transistors and integrated circuits having germanium tin, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a channel region that comprises a germanium tin portion of a fin such that the fin includes a buffer layer disposed over a substrate and the germanium tin portion disposed over the buffer layer.

摘要翻译： 讨论了与具有锗锡的晶体管和集成电路相关的技术，并入这种晶体管的系统及其形成方法。 这种晶体管包括沟道区，其包括鳍的锗锡部分，使得鳍包括设置在衬底上的缓冲层和设置在缓冲层上的锗锡部。

公开(公告)号：EP3123518A1

公开(公告)日：2017-02-01

申请号：EP14887192.4

申请日：2014-03-27

申请人： Intel Corporation

发明人： CEA, Stephen, M. ,  KOTLYAR, Roza ,  KENNEL, Harold, W. ,  GLASS, Glenn, A. ,  MURTHY, Anand, S. ,  RACHMADY, Willy ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66818

摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

摘要翻译： 公开了用于将高迁移率应变通道结合到鳍状NMOS晶体管（例如，诸如双栅极，触发器等的FinFET）中的技术，其中将应力材料包覆到鳍的沟道区域上。 在一个示例性实施例中，锗或硅锗膜被包覆到硅散热片上，以便在翅片的芯中提供期望的拉伸应变，尽管可以使用其它翅片和包层材料。 这些技术与典型的工艺流程兼容，并且包层沉积可以发生在典型工艺流程中的多个位置处。 在各种实施例中，可以以最小宽度（或稍后变薄）形成翅片，以便提高晶体管性能。 在一些实施例中，变薄的翅片还增加穿过包覆翅片的芯的拉伸应变。 在一些情况下，通过添加嵌入式硅外延源和漏极可以进一步增强芯中的应变。

公开(公告)号：EP2920815A1

公开(公告)日：2015-09-23

申请号：EP13854345.9

申请日：2013-06-12

申请人： Intel Corporation

发明人： KOTLYAR, Roza ,  CEA, Stephen M. ,  DEWEY, Gilbert ,  CHU-KUNG, Benjamin ,  AVCI, Uygar E. ,  RIOS, Rafael ,  CHAUDHRY, Anurag ,  LINTON, JR., Thomas D. ,  YOUNG, Ian A. ,  KUHN, Kelin J.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

公开(公告)号：EP4012781A1

公开(公告)日：2022-06-15

申请号：EP21198859.7

申请日：2021-09-24

申请人： INTEL Corporation

发明人： KOTLYAR, Roza ,  BOJARSKI, Stephanie A ,  GEORGE, Hubert C ,  AMIN, Payam ,  KEYS, Patrick H ,  PILLARISETTY, Ravi ,  CAUDILLO, Roman ,  LUETHI, Florian ,  CLARKE, James S

IPC分类号： H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/76 ,  B82Y10/00

摘要： Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. The quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode (113, 117), the gate electrode includes a first conductive gate electrode material (113) proximate to side faces of the gate and a second conductive gate electrode material (117) proximate to a center of the gate, and the first gate material has a different material composition than the second gate material, in particular a different work function.

公开(公告)号：EP3998639A1

公开(公告)日：2022-05-18

申请号：EP21210432.7

申请日：2013-06-12

申请人： INTEL Corporation

发明人： CEA, Stephen M. ,  MURTHY, Anand S. ,  GLASS, Glenn A. ,  AUBERTINE, Daniel B. ,  GHANI, Tahir ,  KAVALIEROS, Jack T. ,  KOTLYAR, Roza

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/165 ,  H01L29/10

摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the builtin stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric / semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric / semiconductor interface.

公开(公告)号：EP3087610A1

公开(公告)日：2016-11-02

申请号：EP13900282.8

申请日：2013-12-23

申请人： Intel Corporation

发明人： AVCI, Uygar E. ,  KOTLYAR, Roza ,  DEWEY, Gilbert ,  CHU-KUNG, Benjamin ,  YOUNG, Ian A.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/125 ,  G11C5/06 ,  H01L29/0669 ,  H01L29/165 ,  H01L29/205 ,  H01L29/7391 ,  H01L29/7831

摘要： Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage.

公开(公告)号：EP2619797A2

公开(公告)日：2013-07-31

申请号：EP11827279.8

申请日：2011-09-19

申请人： Intel Corporation

发明人： CEA, Stephen M. ,  KOTLYAR, Roza ,  KAVALIEROS, Jack T. ,  GILES, Martin D. ,  GHANI, Tahir ,  KUHN, Kelin J. ,  KUHN, Markus ,  ZELICK, Nancy M.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

摘要： A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

公开(公告)号：EP4040503A1

公开(公告)日：2022-08-10

申请号：EP22160872.2

申请日：2011-09-19

申请人： Intel Corporation

发明人： CEA, Stephen M. ,  KOTLYAR, Roza ,  KAVALIEROS, Jack T. ,  GILES, Martin D. ,  GHANI, Tahir ,  KUHN, Kelin J. ,  KUHN, Markus ,  ZELICK, Nancy M.

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/10

摘要： A method and a device made according to the method. The method comprises providing a substrate base portion (102) and a substrate fin (107) extending from the substrate base portion, the fin comprising silicon and germanium; a gate structure (132) covers the fin and epitaxial source and drains (140, 142) comprising germanium are epitaxially grown in recesses formed on both sides of the gate.