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公开(公告)号：EP3382504A1
公开(公告)日：2018-10-03
申请号：EP18158485.5
申请日：2018-02-23
申请人： Intel Corporation
发明人： KOKER, Altug , APPU, Abhishek R. , VEERNAPU, Kiran C. , RAY, Joydeep , VEMBU, Balaji , SURTI, Prasoonkumar , SINHA, Kamal , HOEKSTRA, Eric J. , FU, Wenyin , KABURLASOS, Nikos , BOROLE, Bhushan M. , SCHLUESSLER, Travis T. , SHAH, Ankur N. , KENNEDY, Jonathan
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/3212 , G06F1/3218 , G06F1/3231 , G06F1/324 , G06F3/01 , G06F11/0781 , G06F11/3062 , H04M1/72563 , H04W52/0258 , Y02D10/126 , Y02D70/00 , Y02D70/142 , Y02D70/144 , Y02D70/166 , Y02D70/26
摘要： Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
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公开(公告)号：EP3392873A1
公开(公告)日：2018-10-24
申请号：EP18162140.0
申请日：2018-03-15
申请人： INTEL Corporation
CPC分类号： G06F3/04845 , G06F2203/04803 , G06T1/20 , G09G5/10 , G09G5/363 , G09G2320/0686 , G09G2330/021
摘要： Methods and apparatus relating to techniques for provision of active window rendering optimization and display are described. In an embodiment, a processor is caused to render an active portion of a display device prior to an inactive portion of the display device based at least in part on comparison of a determined size of the active portion of the display device with a threshold value. Furthermore, the active portion of the display device may include a portion of the display device that is being viewed by a user or otherwise a portion of the display device with which a user is interacting. Other embodiments are also disclosed and claimed.
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公开(公告)号：EP4351233A3
公开(公告)日：2024-07-03
申请号：EP24158696.5
申请日：2018-02-23
申请人： INTEL Corporation
发明人： KOKER, Altug , APPU, Abhishek R. , VEERNAPU, Kiran C. , RAY, Joydeep , VEMBU, Balaji , SURTI, Prasoonkumar , SINHA, Kamal , HOEKSTRA, Eric J. , FU, Wenyin , KABURLASOS, Nikos , BOROLE, Bhushan M. , SCHLUESSLER, Travis T. , SHAH, Ankur N. , KENNEDY, Jonathan
CPC分类号： G06F1/3203 , G06F1/324 , H04W52/0258 , Y02D10/00 , Y02D30/70 , H04M1/72448 , G06T1/20
摘要： An apparatus is disclosed with one or more processors including a graphics processing unit, the graphics processing unit including a graphics processing pipeline, and a memory to store data, including graphics data processed by the graphics processing pipeline, wherein the graphics processing unit is to conduct a training session with an application, the training session including a plurality of executions of the application utilizing the graphics processing pipeline, wherein the plurality of executions of the application includes executing the application under a plurality of different operating parameters, a plurality of different hardware configurations, or both, collect performance data for the application during the plurality of executions of the application, generate a performance profile for the application as processed in the graphics processing pipeline based on the collected performance data, train a neural network to configure the graphics processing pipeline based on performance profile data from the performance profile for the application, and utilize the trained neural network to configure the graphics processing pipeline to execute an instance of the application. Furthermore, a method and one or more computer-readable media are disclosed.
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公开(公告)号：EP4351233A2
公开(公告)日：2024-04-10
申请号：EP24158696.5
申请日：2018-02-23
申请人： INTEL Corporation
发明人： KOKER, Altug , APPU, Abhishek R. , VEERNAPU, Kiran C. , RAY, Joydeep , VEMBU, Balaji , SURTI, Prasoonkumar , SINHA, Kamal , HOEKSTRA, Eric J. , FU, Wenyin , KABURLASOS, Nikos , BOROLE, Bhushan M. , SCHLUESSLER, Travis T. , SHAH, Ankur N. , KENNEDY, Jonathan
IPC分类号： H04W52/02
摘要： An apparatus is disclosed with one or more processors including a graphics processing unit, the graphics processing unit including a graphics processing pipeline, and a memory to store data, including graphics data processed by the graphics processing pipeline, wherein the graphics processing unit is to conduct a training session with an application, the training session including a plurality of executions of the application utilizing the graphics processing pipeline, wherein the plurality of executions of the application includes executing the application under a plurality of different operating parameters, a plurality of different hardware configurations, or both, collect performance data for the application during the plurality of executions of the application, generate a performance profile for the application as processed in the graphics processing pipeline based on the collected performance data, train a neural network to configure the graphics processing pipeline based on performance profile data from the performance profile for the application, and utilize the trained neural network to configure the graphics processing pipeline to execute an instance of the application. Furthermore, a method and one or more computer-readable media are disclosed.
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公开(公告)号：EP3396556A1
公开(公告)日：2018-10-31
申请号：EP18159606.5
申请日：2018-03-01
申请人： INTEL Corporation
发明人： VEMBU, Balaji , KOKER, Altug , MASTRONARDE, Josh B. , KABURLASOS, Nikos , APPU, Abhishek R. , JAHAGIRDAR, Sanjeev S. , ASPERHEIM, Eric J. , MAIYURAN, Subramaniam , VEERNAPU, Kiran C. , K, Pattabhiraman , SINHA, Kamal , BOROLE, Bhushan M. , FU, Wenyin , RAY, Joydeep , SURTI, Prasoonkumar , HOEKSTRA, Eric J. , SCHLUESSLER, Travis T. , HURD, Linda L.
IPC分类号： G06F12/0895
CPC分类号： G06F12/0646 , G06F12/0895 , G06F2212/1028 , G06F2212/1044 , G06F2212/1048 , G06F2212/601 , G06F2212/6012 , G06F2212/604 , Y02D10/13
摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.
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公开(公告)号：EP3964927A1
公开(公告)日：2022-03-09
申请号：EP21203463.1
申请日：2018-02-23
申请人： Intel Corporation
发明人： KOKER, Altug , APPU, Abhishek R. , VEERNAPU, Kiran C. , RAY, Joydeep , VEMBU, Balaji , SURTI, Prasoonkumar , SINHA, Kamal , HOEKSTRA, Eric J. , FU, Wenyin , KABURLASOS, Nikos , BOROLE, Bhushan M. , SCHLUESSLER, Travis T. , SHAH, Ankur N. , KENNEDY, Jonathan
摘要： A method executed on an apparatus is disclosed, wherein the method includes collecting one or more pipeline performance metrics associated with one or more stages in a graphics processing pipeline, and adjusting at least one of an operating voltage or an operating frequency of the one or more stages in the graphics pipeline based at least in part on the one or more performance metrics. Furthermore, an apparatus and one or more computer-readable media are also disclosed.
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公开(公告)号：EP3809266A1
公开(公告)日：2021-04-21
申请号：EP20213160.3
申请日：2018-03-23
申请人： INTEL Corporation
发明人： APPU, Abhishek , KOKER, Altug , VEMBU, Balaji , RAY, Joydeep , SINHA, Kamal , SURTI, Prasoonkumar , VEERNAPU, Kiran C. , MAIYURAN, Subramaniam , JAHAGIRDAR, Sanjeev S. , ASPERHEIM, Eric J. , LUEH, Guei-Yuan , PUFFER, David , FU, Wenyin , KABURLASOS, Nikos , BOROLE, Bhushan M. , MASTRONARDE, Josh B. , HURD, Linda L. , SCHLUESSLER, Travis T. , JANCZAK, Tomasz , VENKATESH, Abhishek , XIAO, Kai , GRAJEWSKI, Slawomir
IPC分类号： G06F9/50
摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
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公开(公告)号：EP3396546A1
公开(公告)日：2018-10-31
申请号：EP18163807.3
申请日：2018-03-23
申请人： INTEL Corporation
发明人： SURTI, Prasoonkumar , SRINIVASA, Narayan , CHEN, Feng , RAY, Joydeep , ASHBAUGH, Ben J. , GALOPPO VON BORRIES, Nicolas C. , NURVITADHI, Eriko , VEMBU, Balaji , LIN, Tsung-Han , SINHA, Kamal , BARIK, Rajkishore , BAGHSORKHI, Sara S. , GOTTSCHLICH, Justin E. , KOKER, Altug , SATISH, Nadathur Rajagopalan , AKHBARI, Farshad , KIM, Dukhwan , FU, Wenyin , SCHLUESSLER, Travis T. , MASTRONARDE, Josh B. , HURD, Linda L. , FEIT, John H. , BOLES, Jeffrey S. , LAKE, Adam T. , VAIDYANATHAN, Karthik , BURKE, Devan , MAIYURAN, Subramaniam , APPU, Abhishek R. , MASTRONARDE, Josh B.
CPC分类号： G06T1/20 , G06F8/41 , G06F9/45533 , G06F9/5061 , G06F9/5094 , G06F17/16 , G06F2009/45583
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type
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公开(公告)号：EP3392827A1
公开(公告)日：2018-10-24
申请号：EP18167859.0
申请日：2018-04-17
申请人： INTEL Corporation
发明人： VEMBAR, Deepak S. , KUWAHARA, Atsuo , SAKTHIVEL, Chandrasekaran , VENKATARAMAN, Radhakrishnan , INSKO, Brent E. , KALRA, Anupreet S. , LABBE, Hugues , KOKER, Altug , APODACA, Michael , XIAO, Kai , BOLES, Jeffrey S. , LAKE, Adam T. , CIMINI, David M. , VEMBU, Balaji , OULD-AHMED-VALL, Elmoustapha , KWIATKOWSKI, Jacek , LAWS, Phillip R. , SHAH, Ankur N. , APPU, Abhishek R. , RAY, Joydeep , FU, Wenyin , KABURLASOS, Nikos , SURTI, Prasoonkumar , BOROLE, Bhushan M.
CPC分类号： G06F3/1454 , G06F3/1431 , G06F3/147 , G06T1/20 , G09G3/003 , G09G5/363 , G09G2340/02 , G09G2350/00 , G09G2352/00 , G09G2354/00 , G09G2360/08 , G09G2360/121 , G09G2360/125 , G09G2370/02 , H04L65/4023 , H04L67/38
摘要： An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
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