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公开(公告)号：EP3964927A1
公开(公告)日：2022-03-09
申请号：EP21203463.1
申请日：2018-02-23
申请人： Intel Corporation
发明人： KOKER, Altug , APPU, Abhishek R. , VEERNAPU, Kiran C. , RAY, Joydeep , VEMBU, Balaji , SURTI, Prasoonkumar , SINHA, Kamal , HOEKSTRA, Eric J. , FU, Wenyin , KABURLASOS, Nikos , BOROLE, Bhushan M. , SCHLUESSLER, Travis T. , SHAH, Ankur N. , KENNEDY, Jonathan
摘要： A method executed on an apparatus is disclosed, wherein the method includes collecting one or more pipeline performance metrics associated with one or more stages in a graphics processing pipeline, and adjusting at least one of an operating voltage or an operating frequency of the one or more stages in the graphics pipeline based at least in part on the one or more performance metrics. Furthermore, an apparatus and one or more computer-readable media are also disclosed.
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公开(公告)号：EP3392764A1
公开(公告)日：2018-10-24
申请号：EP18167853.3
申请日：2018-04-17
申请人： INTEL Corporation
发明人： BURKE, Devan , LAKE, Adam T. , BOLES, Jeffrey S. , FEIT, John H. , VAIDYANATHAN, Karthik , APPU, Abhishek R. , RAY, Joydeep , MAIYURAN, Subramaniam , KOKER, Altug , VEMBU, Balaji , RAMADOSS, Murali , SURTI, Prasoonkumar , HOEKSTRA, Eric J. , LIKTOR, Gabor , KENNEDY, Jonathan , GRAJEWSKI, Slawomir , OULD-AHMED-VALL, Elmoustapha
IPC分类号： G06F9/48
CPC分类号： G06T15/005 , G06F9/3836 , G06F9/4881 , G06T15/04 , G06T15/80 , G06T17/10 , G06T17/20
摘要： An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.
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公开(公告)号：EP3392838A1
公开(公告)日：2018-10-24
申请号：EP18161816.6
申请日：2018-03-14
申请人： INTEL Corporation
发明人： APPU, Abhishek R. , SURTI, Prasoonkumar , MYSORE, Srivallaba , DASGUPTA, Subhajit , AKIBA, Hiroshi , HOEKSTRA, Eric J. , HURD, Linda L. , SCHLUESSLER, Travis T. , SCHMIDT, Daren J.
CPC分类号： G06T15/005 , G06F1/3287 , G06F9/54 , G06T1/20 , G06T15/503
摘要： Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.
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公开(公告)号：EP3382504A1
公开(公告)日：2018-10-03
申请号：EP18158485.5
申请日：2018-02-23
申请人： Intel Corporation
发明人： KOKER, Altug , APPU, Abhishek R. , VEERNAPU, Kiran C. , RAY, Joydeep , VEMBU, Balaji , SURTI, Prasoonkumar , SINHA, Kamal , HOEKSTRA, Eric J. , FU, Wenyin , KABURLASOS, Nikos , BOROLE, Bhushan M. , SCHLUESSLER, Travis T. , SHAH, Ankur N. , KENNEDY, Jonathan
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/3212 , G06F1/3218 , G06F1/3231 , G06F1/324 , G06F3/01 , G06F11/0781 , G06F11/3062 , H04M1/72563 , H04W52/0258 , Y02D10/126 , Y02D70/00 , Y02D70/142 , Y02D70/144 , Y02D70/166 , Y02D70/26
摘要： Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
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公开(公告)号：EP4351233A3
公开(公告)日：2024-07-03
申请号：EP24158696.5
申请日：2018-02-23
申请人： INTEL Corporation
发明人： KOKER, Altug , APPU, Abhishek R. , VEERNAPU, Kiran C. , RAY, Joydeep , VEMBU, Balaji , SURTI, Prasoonkumar , SINHA, Kamal , HOEKSTRA, Eric J. , FU, Wenyin , KABURLASOS, Nikos , BOROLE, Bhushan M. , SCHLUESSLER, Travis T. , SHAH, Ankur N. , KENNEDY, Jonathan
CPC分类号： G06F1/3203 , G06F1/324 , H04W52/0258 , Y02D10/00 , Y02D30/70 , H04M1/72448 , G06T1/20
摘要： An apparatus is disclosed with one or more processors including a graphics processing unit, the graphics processing unit including a graphics processing pipeline, and a memory to store data, including graphics data processed by the graphics processing pipeline, wherein the graphics processing unit is to conduct a training session with an application, the training session including a plurality of executions of the application utilizing the graphics processing pipeline, wherein the plurality of executions of the application includes executing the application under a plurality of different operating parameters, a plurality of different hardware configurations, or both, collect performance data for the application during the plurality of executions of the application, generate a performance profile for the application as processed in the graphics processing pipeline based on the collected performance data, train a neural network to configure the graphics processing pipeline based on performance profile data from the performance profile for the application, and utilize the trained neural network to configure the graphics processing pipeline to execute an instance of the application. Furthermore, a method and one or more computer-readable media are disclosed.
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公开(公告)号：EP4030388A1
公开(公告)日：2022-07-20
申请号：EP21214391.1
申请日：2018-03-14
申请人： Intel Corporation
发明人： APPU, Abhishek R. , SURTI, Prasoonkumar , MYSORE, Srivallaba , DASGUPTA, Subhajit , AKIBA, Hiroshi , HOEKSTRA, Eric J. , HURD, Linda L. , SCHLUESSLER, Travis T. , SCHMIDT, Daren J.
摘要： Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API), wherein the alpha channel data is to be routed to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. A first Finite Impulse Response (FIR) filter is coupled to the fixed point blending unit and operates at a lower precision. A second FIR filter is coupled to the fixed point blending unit and operates at a second precision that corresponds to a difference between a higher precision and the lower precision.
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公开(公告)号：EP4351233A2
公开(公告)日：2024-04-10
申请号：EP24158696.5
申请日：2018-02-23
申请人： INTEL Corporation
发明人： KOKER, Altug , APPU, Abhishek R. , VEERNAPU, Kiran C. , RAY, Joydeep , VEMBU, Balaji , SURTI, Prasoonkumar , SINHA, Kamal , HOEKSTRA, Eric J. , FU, Wenyin , KABURLASOS, Nikos , BOROLE, Bhushan M. , SCHLUESSLER, Travis T. , SHAH, Ankur N. , KENNEDY, Jonathan
IPC分类号： H04W52/02
摘要： An apparatus is disclosed with one or more processors including a graphics processing unit, the graphics processing unit including a graphics processing pipeline, and a memory to store data, including graphics data processed by the graphics processing pipeline, wherein the graphics processing unit is to conduct a training session with an application, the training session including a plurality of executions of the application utilizing the graphics processing pipeline, wherein the plurality of executions of the application includes executing the application under a plurality of different operating parameters, a plurality of different hardware configurations, or both, collect performance data for the application during the plurality of executions of the application, generate a performance profile for the application as processed in the graphics processing pipeline based on the collected performance data, train a neural network to configure the graphics processing pipeline based on performance profile data from the performance profile for the application, and utilize the trained neural network to configure the graphics processing pipeline to execute an instance of the application. Furthermore, a method and one or more computer-readable media are disclosed.
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公开(公告)号：EP3396556A1
公开(公告)日：2018-10-31
申请号：EP18159606.5
申请日：2018-03-01
申请人： INTEL Corporation
发明人： VEMBU, Balaji , KOKER, Altug , MASTRONARDE, Josh B. , KABURLASOS, Nikos , APPU, Abhishek R. , JAHAGIRDAR, Sanjeev S. , ASPERHEIM, Eric J. , MAIYURAN, Subramaniam , VEERNAPU, Kiran C. , K, Pattabhiraman , SINHA, Kamal , BOROLE, Bhushan M. , FU, Wenyin , RAY, Joydeep , SURTI, Prasoonkumar , HOEKSTRA, Eric J. , SCHLUESSLER, Travis T. , HURD, Linda L.
IPC分类号： G06F12/0895
CPC分类号： G06F12/0646 , G06F12/0895 , G06F2212/1028 , G06F2212/1044 , G06F2212/1048 , G06F2212/601 , G06F2212/6012 , G06F2212/604 , Y02D10/13
摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.
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公开(公告)号：EP3382533A1
公开(公告)日：2018-10-03
申请号：EP18160823.3
申请日：2018-03-08
申请人： INTEL Corporation
发明人： APPU, Abhishek R. , KOKER, Altug , RAY, Joydeep , SINHA, Kamal , VEERNAPU, Kiran C. , MAIYURAN, Subramaniam , SURTI, Prasoonkumar , LUEH, Guei-Yuan , PUFFER, David , PAL, Supratim , HOEKSTRA, Eric J. , SCHLUESSLER, Travis T. , HURD, Linda L.
CPC分类号： G06F9/3012 , G06F9/30014 , G06F9/30105 , G06F9/30123 , G06F9/30138 , G06F9/384 , G06F9/3851 , G06F9/3885 , G06F9/3891 , G06F9/462 , G06F2212/452 , G06T1/20 , G06T1/60 , G06T15/005 , G06T2210/12 , G06T2210/52 , G09G5/363
摘要： In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.
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公开(公告)号：EP3198552A1
公开(公告)日：2017-08-02
申请号：EP15843700.4
申请日：2015-09-09
申请人： Intel Corporation
CPC分类号： G06T11/00 , G06T1/20 , G06T1/60 , G06T15/005
摘要： An apparatus and method for pixel hashing. For example, one embodiment of a method comprises: determining X and Y coordinates for a pixel block to be processed; performing a lookup in a data structure indexed based on the X and Y coordinates of the pixel block, the lookup identifying an entry in the data structure corresponding to the X and Y coordinates of the pixel block; reading information from the entry identifying an execution cluster to process the pixel block; and executing the pixel block by the execution cluster.
摘要翻译： 一种像素散列的装置和方法。 例如，方法的一个实施例包括：确定要处理的像素块的X和Y坐标; 在基于像素块的X和Y坐标索引的数据结构中执行查找，所述查找标识数据结构中对应于像素块的X和Y坐标的条目; 从标识执行簇的条目中读取信息以处理像素块; 并由执行群执行像素块。
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