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    SPLIT T-CHAIN MEMORY COMMAND AND ADDRESS BUS TOPOLOGY
    2.
    发明授权
    SPLIT T-CHAIN MEMORY COMMAND AND ADDRESS BUS TOPOLOGY 有权
    指挥ADRESSENBUSTOPOLOGIE分裂-T连锁店

    公开(公告)号：EP1652097B1

    公开(公告)日：2008-02-27

    申请号：EP04780114.7

    申请日：2004-08-04

    Applicant: INTEL CORPORATION

    Inventor： LEDDIGE, Michael ,  MCCALL, James

    IPC: G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/4239 ,  G11C5/04

    Abstract: Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA is divided on the motherboard and a CA signal component routed to each of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal component on each DIMM is then routed sequentially through each dynamic random access memory (DRAM) chip on the respective DIMM. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM. In an alternative embodiment, the CA signal is terminated on the die at the last DRAM of each respective DIMM.

    SPLIT T-CHAIN MEMORY COMMAND AND ADDRESS BUS TOPOLOGY
    3.
    发明公开
    SPLIT T-CHAIN MEMORY COMMAND AND ADDRESS BUS TOPOLOGY 有权
    指挥ADRESSENBUSTOPOLOGIE分裂-T连锁店

    公开(公告)号：EP1652097A2

    公开(公告)日：2006-05-03

    申请号：EP04780114.7

    申请日：2004-08-04

    Applicant: INTEL CORPORATION

    Inventor： LEDDIGE, Michael ,  MCCALL, James

    IPC: G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/4239 ,  G11C5/04

    Abstract: Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA is divided on the motherboard and a CA signal component routed to each of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal component on each DIMM is then routed sequentially through each dynamic random access memory (DRAM) chip on the respective DIMM. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM. In an alternative embodiment, the CA signal is terminated on the die at the last DRAM of each respective DIMM.

    CIRCULATOR CHAIN MEMORY COMMAND AND ADDRESS BUS TOPOLOGY
    4.
    发明授权
    CIRCULATOR CHAIN MEMORY COMMAND AND ADDRESS BUS TOPOLOGY 有权
    循环连锁店指挥和-ADRESSENBUSTOPOLOGIE

    公开(公告)号：EP1678622B1

    公开(公告)日：2008-09-24

    申请号：EP04783341.3

    申请日：2004-09-03

    Applicant: Intel Corporation

    Inventor： LEDDIGE, Michael ,  MCCALL, James

    IPC: G11C5/00

    CPC classification number: G11C8/12 ,  G11C5/063 ,  G11C7/1066

    Abstract: Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA signal is routed to a first of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal is then divided into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM. The CA signal components are then recombined and routed to the second DIMM. The recombined CA signal is then divided again into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM and the CA signal components are then recombined. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM.

    CIRCULATOR CHAIN MEMORY COMMAND AND ADDRESS BUS TOPOLOGY
    9.
    发明公开
    CIRCULATOR CHAIN MEMORY COMMAND AND ADDRESS BUS TOPOLOGY 有权
    循环连锁店指挥和-ADRESSENBUSTOPOLOGIE

    公开(公告)号：EP1678622A2

    公开(公告)日：2006-07-12

    申请号：EP04783341.3

    申请日：2004-09-03

    Applicant: INTEL CORPORATION

    Inventor： LEDDIGE, Michael ,  MCCALL, James

    IPC: G06F13/28

    CPC classification number: G11C8/12 ,  G11C5/063 ,  G11C7/1066

    Abstract: Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA signal is routed to a first of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal is then divided into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM. The CA signal components are then recombined and routed to the second DIMM. The recombined CA signal is then divided again into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM and the CA signal components are then recombined. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM.

    VIA PAD GEOMETRY SUPPORTING UNIFORM TRANSMISSION LINE STRUCTURES
    10.
    发明公开
    VIA PAD GEOMETRY SUPPORTING UNIFORM TRANSMISSION LINE STRUCTURES 有权
    威盛PAD几何支持均匀传输线结构

    公开(公告)号：EP1029431A1

    公开(公告)日：2000-08-23

    申请号：EP98943307.3

    申请日：1998-08-20

    Applicant: INTEL CORPORATION

    Inventor： LEDDIGE, Michael ,  SPRIETSMA, John

    IPC: H05K7/02

    CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09381 ,  H05K2201/09727

    Abstract: A connector (400) for coupling high frequency signals between devices includes a substrate having an array of vias (410) for coupling a reference voltage to reference voltages traces (460) that extend along the substrate surface between the devices. Signal traces (430) including device pads (434) for coupling signals to and from the devices alternate with the reference voltage traces (460). The widths of the reference voltage traces (460) are varied to maintain a substantially constant separation between the reference voltage trace (460) and an adjacent signal trace (430).

    Abstract translation: 用于在器件之间耦合高频信号的连接器（400）包括具有用于将参考电压耦合到在器件之间沿着衬底表面延伸的参考电压迹线（460）的衬底阵列的衬底（410）。 包括用于耦合去往和来自装置的信号的装置垫（434）的信号迹线（430）与参考电压迹线（460）交替。 参考电压迹线（460）的宽度被改变以维持参考电压迹线（460）与相邻信号迹线（430）之间的基本上恒定的间隔。

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