公开(公告)号：EP1384256B1

公开(公告)日：2009-07-08

申请号：EP02731605.8

申请日：2002-04-30

申请人： International Business Machines Corporation

发明人： GATES, Stephen, McConnell ,  MURRAY, Christopher, B. ,  NITTA, Satyanarayana, V. ,  PURUSHOTHAMAN, Sampath

IPC分类号： H01L21/316

CPC分类号： H01L21/02112 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/31695 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/24149 ,  Y10T428/24917 ,  Y10T428/249953 ,  Y10T428/249958 ,  Y10T428/249967 ,  Y10T428/249969 ,  Y10T428/249978 ,  Y10T428/249979 ,  Y10T428/249987 ,  Y10T428/24999 ,  Y10T428/249991 ,  Y10T428/26 ,  Y10T428/31663 ,  H01L2924/00

摘要： A porous, low-k dielectric film that has good mechanical properties as well as a method of fabricating the film and the use of the film as a dielectric layer between metal wiring features are provided. The porous, low-k dielectric film includes a first phase of monodispersed pores having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially located on sites of a three-dimensional periodic lattice; and a second phase which is solid surrounding the first phase. Specifically, the second phase of the film includes (i) an ordered element that is composed of nanoparticles having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially arranged on sites of a three-dimensional periodic lattice, and (ii) a disordered element comprised of a dielectric material having a dielectric constant of about 2.8 or less.

公开(公告)号：EP1761946A2

公开(公告)日：2007-03-14

申请号：EP05753989.2

申请日：2005-05-23

申请人： International Business Machines Corporation

发明人： HUANG, Elbert, E. ,  KIM, Hyungjun ,  MILLER, Robert, D. ,  NITTA, Satyanarayana, V. ,  PURUSHOTHAMAN, Sampath

IPC分类号： H01L21/302 ,  H01L21/311

CPC分类号： H01L21/76808 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/3121 ,  H01L21/3125 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures are fabricated by methods that comprise depositing a thin conformal passivation dielectric and/or diffusion barrier cap and/or hard mask by an atomic layer deposition or supercritical fluid based process.

公开(公告)号：EP1384256A2

公开(公告)日：2004-01-28

申请号：EP02731605.8

申请日：2002-04-30

申请人： International Business Machines Corporation

发明人： GATES, Stephen, McConnell ,  MURRAY, Christopher, B. ,  NITTA, Satyanarayana, V. ,  PURUSHOTHAMAN, Sampath

IPC分类号： H01L21/316

CPC分类号： H01L21/02112 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/31695 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/24149 ,  Y10T428/24917 ,  Y10T428/249953 ,  Y10T428/249958 ,  Y10T428/249967 ,  Y10T428/249969 ,  Y10T428/249978 ,  Y10T428/249979 ,  Y10T428/249987 ,  Y10T428/24999 ,  Y10T428/249991 ,  Y10T428/26 ,  Y10T428/31663 ,  H01L2924/00

摘要： A porous, low-k dielectric film that has good mechanical properties as well as a method of fabricating the film and the use of the film as a dielectric layer between metal wiring features are provided. The porous, low-k dielectric film includes a first phase of monodispersed pores having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially located on sites of a three-dimensional periodic lattice; and a second phase which is solid surrounding the first phase. Specifically, the second phase of the film includes (i) an ordered element that is composed of nanoparticles having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially arranged on sites of a three-dimensional periodic lattice, and (ii) a disordered element comprised of a dielectric material having a dielectric constant of about 2.8 or less.

公开(公告)号：EP1812961A1

公开(公告)日：2007-08-01

申请号：EP04796562.9

申请日：2004-10-27

申请人： International Business Machines Corporation

发明人： CHAKRAPANI, Nirupama ,  COLBURN, Matthew, E. ,  DIMITRAKOPOULOS, Christos, D. ,  NITTA, Satyanarayana, V. ,  PFEIFFER, Dirk ,  PURUSHOTHAMAN, Sampath

IPC分类号： H01L21/31 ,  H01L21/316

CPC分类号： H01L21/31058 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826

摘要： Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the S:L atoms in the network. Si-R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si-R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)xSiR'y where X and Y are integers from 1 to 3 and 3 to I respectively, and where R and R' are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.

公开(公告)号：EP1371091A1

公开(公告)日：2003-12-17

申请号：EP01990800.3

申请日：2001-12-04

申请人： International Business Machines Corporation

发明人： GATES, Stephen, McConnell ,  HEDRICK, Jeffrey, Curtis ,  NITTA, Satyanarayana, V. ,  PURUSHOTHAMAN, Sampath ,  TYBERG, Christy, Sensenich

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. The control over the conductor resistance is obtained using a buried etch stop layer (56) having a second atomic composition located between the line and via dielectric layers (54', 58') of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask (60) which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

公开(公告)号：EP1371090A1

公开(公告)日：2003-12-17

申请号：EP01990106.5

申请日：2001-12-10

申请人： International Business Machines Corporation

发明人： GATES, Stephen, McConnell ,  HEDRICK, Jeffrey, Curtis ,  NITTA, Satyanarayana, V. ,  PURUSHOTHAMAN, Sampath ,  TYBERG, Christy, Sensenich

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76835 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/76811

摘要： A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics. Moreover, the spun-on dielectrics of the hybrid low-k dielectric have distinctly different atomic compositions enabling control over the conductor resistance using the bottom spun-on dielectric (i.e., via dielectric) as an inherent etch stop layer for the upper spun-on dielectric (i.e., line dielectric).