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1.发明公开Process for producing transistors having independently adjustable parameters 审中-公开一种用于晶体管的与独立的可调参数的制造过程
公开(公告)号：EP1071125A3
公开(公告)日：2005-06-01
申请号：EP00114376.7
申请日：2000-07-05
IPC分类号： H01L21/336 , H01L29/49 , H01L21/8238
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823807 , H01L29/66492 , H01L29/66537 , H01L29/66583
摘要： The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer. As a result, the S-D junctions can be doped independently of the gate conductor doping, more easily allowing a variety of MOSFET structures.
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2.发明公开Process for producing transistors having independently adjustable parameters 审中-公开一种用于晶体管的与独立的可调参数的制造过程
公开(公告)号：EP1071125A2
公开(公告)日：2001-01-24
申请号：EP00114376.7
申请日：2000-07-05
IPC分类号： H01L21/336 , H01L29/49 , H01L21/8238
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823807 , H01L29/66492 , H01L29/66537 , H01L29/66583
摘要： The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer. As a result, the S-D junctions can be doped independently of the gate conductor doping, more easily allowing a variety of MOSFET structures.
摘要翻译： 用于制造半导体器件的方法的规则：如MOSFET的被修改，以提供双功函数掺杂继常规栅侧壁氧化步骤，大大降低热预算和硼渗透的担忧。 热预算的关注被进一步显着，同时保持低的薄层电阻值，其允许降低了的间隙的纵横比的器件结构减小。 从而减小的间隙的纵横比放宽了对高度可回流的介电材料的需求，并且因此便于使用成角度的源极 - 漏极（S-D）和含卤素的注入的。 这样提供了一种用于制造MOSFET沟道，横向掺杂分布，其抑制短沟道效应，而对热载流子效应提供低S-D结电容和漏电流，以及免疫的新颖结构和工艺。 因此这提供减少在接触柱到栅导体的电容的电势，由于无边界接触可以与氧化物栅极侧壁间隔物来形成。 作为结果，S-D结能够掺杂栅导体的掺杂，更方便地允许各种MOSFET结构中的unabhängig。
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3.发明公开
公开(公告)号：EP0929101A1
公开(公告)日：1999-07-14
申请号：EP98310525.5
申请日：1998-12-21
发明人： Bronner, Gary Bela , Gambino, Jeffrey P. , Mandelman, Jack A. , Radens, Carl J. , Tonti, William Robert
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/28 , H01L21/225
CPC分类号： H01L21/28035 , H01L21/82345
摘要： Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.
摘要翻译： 通过在第一导电类型的栅极结构的至少一个侧壁上掺杂选择数量的具有自对准绝缘层的栅极结构的结构，从而提供栅极结构的阵列，从而提供一些栅极结构，从而提供双功能掺杂 掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的导电类型。 还提供了栅极结构的阵列，由此各个栅极结构在其顶部部分包含自对准绝缘层，并且其中一些栅极结构被掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的 导电类型。
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4.发明公开
公开(公告)号：EP0817251A1
公开(公告)日：1998-01-07
申请号：EP97304053.8
申请日：1997-06-11
IPC分类号： H01L21/3105 , H01L21/316
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02129 , H01L21/02211 , H01L21/31051 , H01L21/31625
摘要： A process is provided for the low temperature deposition of a thin film of borophosphosilicate glass (BPSG) for use in semiconductor devices, such as DRAMs. The process includes utilizing R-OH groups as reagents to provide additional -OH groups so that an intermediate {Si(OH) 4 } n is formed having superior reflow properties, allowing the annealing and reflow steps to occur at temperatures less than 750°C, which is the current processing temperature.
摘要翻译： 提供了用于半导体器件（例如DRAM）中的硼磷硅玻璃（BPSG）薄膜的低温沉积的工艺。 该方法包括使用R-OH基团作为试剂以提供额外的-OH基团，从而形成具有优异回流性能的中间体äSi（OH）4ün，使退火和回流步骤在低于750℃的温度下发生， 当前加工温度。
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5.发明授权Method of providing low-resistance salicide fill for trench capacitors 有权一种用于电容器严重Salizidfüllung低电阻过程
公开(公告)号：EP0967643B1
公开(公告)日：2006-12-13
申请号：EP99304729.9
申请日：1999-06-17
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
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公开(公告)号：EP1137063A2
公开(公告)日：2001-09-26
申请号：EP01302653.9
申请日：2001-03-22
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10873
摘要： In one aspect, the present invention discloses a transistor device (see e.g., Figure 3) that includes first and second source/drain regions 124a and 126 disposed in a semiconductor body 122 and separated by a channel region 128a. A dielectric layer 134a overlies the channel region 128a and a gate electrode 130a/132a overlies the dielectric layer 134a. In the preferred embodiment, the gate electrode includes a polysilicon layer 130a that extends a first lateral distance over the dielectric layer and a silicide layer 132a that extends a second lateral distance over the first polysilicon layer. In this example, the first lateral distance is greater than the second lateral distance.
摘要翻译： 本发明公开了一对相邻的DRAM单元（120a，120b）的晶体管器件（114a，114b），它包括设置在半导体本体（122）中的第一和第二源/漏区（124a和126） 通道区域（128a）。 电介质层（134a）覆盖在沟道区（128a）上，栅电极（130a / 132a）覆盖在电介质层（134a）上。 在优选实施例中，栅电极包括在电介质层上延伸第一横向距离的多晶硅层（130a）和在第一多晶硅层上延伸第二横向距离的硅化物层（132a）。 在该示例中，第一横向距离大于第二横向距离。 导体（132）和位线接触（142）之间的较大间隔减小了位线（160）和字线（130/132）之间的寄生电容。
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7.发明公开Low-resistance salicide fill for trench capacitors 有权Verfahren zurSalizidfüllungmit Niedrigem WiderstandfürGrabenkondensatoren
公开(公告)号：EP0967643A2
公开(公告)日：1999-12-29
申请号：EP99304729.9
申请日：1999-06-17
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.
摘要翻译： 使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元格和/或减少的单元访问时间。 本发明的沟槽电容器特别可用作DRAM存储单元的组件。
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8.发明公开Method of making an integrated circuit comprising forming spacers from an interlevel dielectric layer 审中-公开一种用于生产包括电介质中间层的间隔物的形成的集成电路处理
公开(公告)号：EP0905773A2
公开(公告)日：1999-03-31
申请号：EP98307905.4
申请日：1998-09-29
IPC分类号： H01L21/8242 , H01L21/8234
CPC分类号： H01L27/10844 , H01L21/823418
摘要： An efficient method of forming deep junction implants in one region without affecting the implant of a second region of an integrated circuit is provided. This is achieved by forming spacers of deep junction devices with the same material used to fill the gaps of shallow junction devices.
摘要翻译： 被提供，而不会影响集成电路的第二区域（130）的植入物形成在一个区域（110）深结注入的方法。 这是通过深结器件（115）与用于填充浅结器件（135）的间隙中的材料相同的材料（180）的形成间隔物（182）来实现的。
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9.发明公开Process for controlling the height of a stud intersecting an interconnect 审中-公开过程用于控制接触短截线的高度上，横跨连接平面
公开(公告)号：EP0929100A3
公开(公告)日：1999-09-15
申请号：EP98310217.9
申请日：1998-12-14
IPC分类号： H01L21/768
CPC分类号： H01L21/76838 , H01L21/76816 , H01L21/76885 , H01L21/76897
摘要： Electrical interconnection with studs is formed by depositing conductive stud material in contact holes in a dielectric layer; patterning the conductive stud material and removing a shallow portion of the dielectric layer surrounding the stud material; depositing a thin layer of dielectric material over the conductive stud and first dielectric layer; forming a trench in the dielectric layers and over the top of the stud material; and depositing conductive material in the trench.
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公开(公告)号：EP0929099A3
公开(公告)日：1999-09-08
申请号：EP98310213.8
申请日：1998-12-14
发明人： Arndt, Kenneth C. , Conti, Richard A. , Dobuzinski, David M. , Economikos, Laertis , Gambino, Jeffrey P. , Hoh, Peter D. , Narayan, Chandrasekhar
IPC分类号： H01L21/768 , H01L21/3213
CPC分类号： H01L21/76804 , H01L21/32136 , H01L21/76835 , H01L21/76885
摘要： Stresses commonly induced in dielectrics of integrated circuits manufactured using metal patterning methods, can be reduced by rounding the lower corners associated with features formed as part of the integrated circuit before applying the outer layer. For metal lines patterned by RIE, corners can be rounded using a two-step metal etching process: a first step producing a vertical sidewall and a second step tapering lower portions of the vertical sidewall or producing a tapered spacer along its lower portions. This produces a rounded bottom corner which improves the step coverage of the overlying dielectric, and eliminates the potential for cracks. For metal lines patterned by damascene, corners can be rounded using a two-step trench etching process: a first step producing a vertical sidewall, and a second step producing a tapered sidewall along its lower portions.
摘要翻译： 在使用金属图案化方法制造的集成电路的电介质中通常引起的应力可以通过在施加外层之前将与作为集成电路的一部分形成的特征相关联的下拐角四舍五入来减小。 对于通过RIE图案化的金属线，拐角可以使用两步金属蚀刻工艺来圆化：产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细或沿着其下部产生锥形间隔物的第二步骤。 这产生了一个圆形的底部拐角，它改善了上覆电介质的台阶覆盖，并消除了裂纹的可能性。 对于通过镶嵌图案化的金属线，角部可以使用两步式沟槽蚀刻工艺来圆化：产生垂直侧壁的第一步骤和沿着其下部部分产生锥形侧壁的第二步骤。
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