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公开(公告)号：EP0905785A3
公开(公告)日：2003-08-13
申请号：EP98307876.7
申请日：1998-09-29
IPC分类号： H01L27/108 , G11C11/409 , G11C8/00 , H01L27/105 , H01L21/8242 , G11C8/14
CPC分类号： H01L27/10891 , G11C7/18 , G11C11/4097 , H01L27/10861
摘要： Disclosed is a high density semiconductor memory having diagonal bit lines and a dual word line configuration with highly efficient use of chip area. In an exemplary embodiment, the semiconductor memory includes a memory cell array (10) of memory cells arranged in rows and columns, and a plurality of diagonal bit lines (BLP 1 -BLP N ) arranged in a pattern that changes horizontal direction along the memory cell array to facilitate access to said memory cells. True bit lines are periodically twisted at locations (33) in the vertical plane with the associated complementary bit lines. The bit lines are arranged non-orthogonal to a plurality of dual word lines (WL 1 -WL M ), where each dual word line includes a master word line (MWL i ) at a first layer and a plurality of local word lines (LWL 1 -LWL X ) at a second layer. The local word lines are connected to the master word line of a common row via a plurality of spaced electrical connections (29), e.g., electrical contacts in a "stitched" architecture, and each local word line is connected to plural memory cells (MC). The electrical contacts or stitches (29) that connect the local word lines to the associated master word line follow the same zigzag pattern in the horizontal plane as the bit it lines. Accordingly, the area penalty of the segmented architecture of FIG. 1A is largely eliminated.
摘要翻译： 几个对角位线（BLP1-BLPN）以折叠或开放位线配置布置，沿着存储单元阵列（10）改变水平方向，以便于访问存储单元。 几个双字线（WL1-WLM）布置成与位线非正交。 双字线包括第一层的主字线（MWLi）和第二层的第二本地字线（LWL1-LWLX）。 本地字线通过几个电触点（29）连接到公共行的主字线。 - 存储单元阵列由排列成行和列的多个存储单元（MC）组成。 在位线配置的水平方向发生变化的半导体存储器的每个区域（33）处的折叠位线发生垂直扭曲。 电触点以交替的行布置，沿着存储单元阵列在水平方向上具有变化。 存储单元是6F2单元，其中F表示存储元件的最小特征尺寸。 技术聚焦 - 冶金 - 电触点由铝材料组成。
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公开(公告)号：EP0889528A3
公开(公告)日：2002-01-16
申请号：EP98305124.4
申请日：1998-06-29
IPC分类号： H01L27/108 , G11C11/4097
CPC分类号： H01L27/10805 , H01L27/10882 , Y10S257/905 , Y10S257/907
摘要： A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer. The upper metal first bit line portion is coupled to the lower first metal bit line portion by a first contact through the dielectric layer. The first contact is disposed above one of the active areas.
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公开(公告)号：EP0905785A2
公开(公告)日：1999-03-31
申请号：EP98307876.7
申请日：1998-09-29
IPC分类号： H01L27/108 , G11C11/409 , G11C8/00 , H01L27/105
CPC分类号： H01L27/10891 , G11C7/18 , G11C11/4097 , H01L27/10861
摘要： Disclosed is a high density semiconductor memory having diagonal bit lines and a dual word line configuration with highly efficient use of chip area. In an exemplary embodiment, the semiconductor memory includes a memory cell array (10) of memory cells arranged in rows and columns, and a plurality of diagonal bit lines (BLP 1 -BLP N ) arranged in a pattern that changes horizontal direction along the memory cell array to facilitate access to said memory cells. The bit lines are arranged non-orthogonal to a plurality of dual word lines (WL 1 -WL M ), where each dual word line includes a master word line (MWL i ) at a first layer and a plurality of local word lines (LWL 1 -LWL X ) at a second layer. The local word lines are connected to the master word line of a common row via a plurality of spaced electrical connections (29), e.g., electrical contacts in a "stitched" architecture, and each local word line is connected to plural memory cells (MC). The electrical connections run in substantially the same pattern along the memory cell array as the bit lines.
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公开(公告)号：EP0982777B1
公开(公告)日：2004-09-15
申请号：EP99306023.5
申请日：1999-07-29
发明人： Hoenigschmid, Heinz , Netis, Dmitry
IPC分类号： H01L27/105 , H01L27/02
CPC分类号： H01L27/108 , H01L27/105
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公开(公告)号：EP0889528A2
公开(公告)日：1999-01-07
申请号：EP98305124.4
申请日：1998-06-29
IPC分类号： H01L27/108
CPC分类号： H01L27/10805 , H01L27/10882 , Y10S257/905 , Y10S257/907
摘要： A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer. The upper metal first bit line portion is coupled to the lower first metal bit line portion by a first contact through the dielectric layer. The first contact is disposed above one of the active areas.
摘要翻译： 该阵列由设置在有源区域（522）中的存储单元形成，每个存储单元可由一组相应的字线和位线寻址。 字线以预定角度倾斜到位线。 阵列中的第一条存储单元包括通过电介质层形成在下金属层上的上金属层。 在下金属层中形成位线（BL1），并连接到形成第一条带的存储单元。 在上金属层（bBL1）中形成位线，并通过设置在电介质层中的有源区（522）上方的触点（528）与下金属位线连接。
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6.发明公开Method of operation of dynamic random access memory 有权Betriebsverfahrenfürdynamischen Direktzugriffspeicher
公开(公告)号：EP0928006A3
公开(公告)日：2000-08-09
申请号：EP98310641.0
申请日：1998-12-23
IPC分类号： G11C11/407 , G11C5/14
CPC分类号： G11C11/4074 , G11C5/14 , G11C5/141
摘要： Reduced current consumption in a DRAM during standby mode is achieved by switching off the power source that is connected to, for example, the n-well.
摘要翻译： 在待机模式下DRAM的电流消耗降低是通过关断连接到例如n阱的电源实现的。
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7.发明公开Wordline driver circuit using ring-shaped devices 有权Wortleitungstreiberschaltung mitringförmigerVorrichtung
公开(公告)号：EP0982777A1
公开(公告)日：2000-03-01
申请号：EP99306023.5
申请日：1999-07-29
发明人： Hoenigschmid, Heinz , Netis, Dmitry
IPC分类号： H01L27/105 , H01L27/02
CPC分类号： H01L27/108 , H01L27/105
摘要： An arrangement of enhanced drivability transistors is disclosed herein which includes a plurality of conductor patterns, wherein the conductor patterns include ring-shaped portions which enclose device diffusion contacts and the ring-shaped portions form the gate conductors of insulated gate field effect transistors (IGFETs).
摘要翻译： 本文公开了一种增强的驱动力晶体管的布置，其包括多个导体图案，其中导体图案包括包围器件扩散接触的环形部分，并且环形部分形成绝缘栅场效应晶体管（IGFET）的栅极导体， 。
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公开(公告)号：EP0928006A2
公开(公告)日：1999-07-07
申请号：EP98310641.0
申请日：1998-12-23
IPC分类号： G11C11/407 , G11C5/14
CPC分类号： G11C11/4074 , G11C5/14 , G11C5/141
摘要： Reduced current consumption in a DRAM during standby mode is achieved by switching off the power source that is connected to, for example, the n-well.
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公开(公告)号：EP0928006B1
公开(公告)日：2004-03-31
申请号：EP98310641.0
申请日：1998-12-23
IPC分类号： G11C11/407 , G11C5/14
CPC分类号： G11C11/4074 , G11C5/14 , G11C5/141
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10.发明公开Method for optical proximity correction 有权Methode und System zur Korrektur von optischen Naheffekten（OPC）
公开(公告)号：EP1094366A1
公开(公告)日：2001-04-25
申请号：EP00309198.0
申请日：2000-10-19
CPC分类号： G03F7/70441 , G03F1/36
摘要： A method, and a system for employing the method, for providing a modified optical proximity correction (OPC) for correcting distortions of pattern lines on a semiconductor circuit wafer. The method comprises producing a mask having one or more pattern regions, and producing the semiconductor circuit wafer from the mask. The pattern regions include one or more non-edge pattern regions located adjacent to other of the non-edge pattern regions on the mask. The pattern regions further include one or more edge pattern regions located at or near an area on the mask not having the other non-edge pattern regions. The edge pattern regions have widths calculated to minimize the variance in dimensions between one or more pattern lines on the semiconductor circuit wafer formed from them and one or more pattern lines on the semiconductor circuit wafer formed from the non-edge pattern regions. The distances between any two of the pattern regions are calculated to minimize the variance in dimensions between the one or more pattern lines formed from the edge pattern regions and the one or more pattern lines formed from the non-edge pattern regions. The above producing step includes producing the semiconductor circuit wafer from the mask having the pattern lines formed from the non-edge pattern regions and having the pattern lines formed from the edge pattern regions, where the pattern lines formed from the non-edge regions are permitted to differ in distances between them.
摘要翻译： 一种用于采用该方法的方法和系统，用于提供用于校正半导体电路晶片上的图案线的失真的修改的光学邻近校正（OPC）。 该方法包括制备具有一个或多个图案区域的掩模，以及从掩模制造半导体电路晶片。 图案区域包括与掩模上的其他非边缘图案区域相邻的一个或多个非边缘图案区域。 图案区域还包括位于不具有其它非边缘图案区域的掩模上的区域附近或附近的一个或多个边缘图案区域。 边缘图案区域具有计算的宽度，以使由其形成的半导体电路晶片上的一个或多个图案线与由非边缘图案区域形成的半导体电路晶片上的一个或多个图案线之间的尺寸变化最小化。 计算任何两个图案区域之间的距离，以使从由边缘图案区域形成的一个或多个图案线和由非边缘图案区域形成的一个或多个图案线之间的尺寸变化最小化。 上述制造步骤包括从具有由非边缘图案区形成的图形线的掩模制造半导体电路晶片，并且具有由边缘图案区形成的图形线，其中从非边缘区域形成的图案线被允许 它们之间的距离不同。
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