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    Heterojunction bipolar transistor and method for fabricating the same
    1.
    发明公开
    Heterojunction bipolar transistor and method for fabricating the same 审中-公开
    Heteroübergangsbipolartransistor和Verfahren zu dessen Herstellung

    公开(公告)号：EP1965431A2

    公开(公告)日：2008-09-03

    申请号：EP08011439.0

    申请日：2000-06-21

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Takagi, Takeshi ,  Yuki, Koichiro ,  Toyoda, Kenji ,  Kanzawa, Yoshihiko

    IPC分类号： H01L29/737 ,  H01L29/161 ,  H01L29/165 ,  H01L21/331

    CPC分类号： H01L29/7378 ,  H01L29/161 ,  H01L29/66242

    摘要： A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

    摘要翻译： 通过依次堆叠Si集电极层，SiGeC基极层和Si发射极层来制造异质结双极晶体管。 通过使Si集电体层的SiGeC基底层中的晶格应变量为1.0％以下，带隙可以窄于传统的实际SiGe（Ge含量为约10％）的带隙，并且良好 结晶可在热处理后保持。 结果，可以实现不具有实际不便的窄带隙基。

    Heterojunction bipolar transistor and method for fabricating the same
    4.
    发明公开
    Heterojunction bipolar transistor and method for fabricating the same 有权
    Heteroübergangsbipolartransistor和Verfahren zu dessen Herstellung

    公开(公告)号：EP1065728A3

    公开(公告)日：2001-08-08

    申请号：EP00113276.0

    申请日：2000-06-21

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Takagi, Takeshi ,  Yuki, Koichiro ,  Toyoda, Kenji ,  Kanzawa, Yoshihiko

    IPC分类号： H01L29/737 ,  H01L29/161 ,  H01L29/165 ,  H01L21/331

    CPC分类号： H01L29/7378 ,  H01L29/161 ,  H01L29/66242

    摘要： A heterojunction bipolar transistor comprises Si collector layer (3b), a SiGeC base layer (8a) and a Si emitter layer (9) stacked in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap of the SiGeC base layer can be narrower than the band gap of the conventional SiGe base layer having a Ge content of about 10%, and good crystal quality can be maintained after a heat treatment.

    摘要翻译： 异质结双极晶体管包括依次堆叠的Si集电极层（3b），SiGeC基极层（8a）和Si发射极层（9）。 通过使Si集电体层的SiGeC基底层中的晶格应变量为1.0％以下，SiGeC基极层的带隙可以窄于具有Ge含量为约的常规SiGe基底层的带隙 10％，并且在热处理后可以保持良好的晶体质量。

    Semiconductor device comprising a heterostructure MIS field-effect transistor having a strained channel layer
    5.
    发明公开
    Semiconductor device comprising a heterostructure MIS field-effect transistor having a strained channel layer 审中-公开
    具有两个异质结场效应晶体管的互补半导体器件具有应变沟道层

    公开(公告)号：EP0921575A2

    公开(公告)日：1999-06-09

    申请号：EP98122863.8

    申请日：1998-12-02

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Takagi, Takeshi

    IPC分类号： H01L29/778 ,  H01L29/78 ,  H01L29/165 ,  H01L29/161

    CPC分类号： H01L29/7786 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/7782 ,  H01L29/802

    摘要： A MISFET having extremely high mobility comprising a first silicon layer (Si layer)(12), a silicon layer containing carbon (Si 1-y C y layer)(13) and an optional, second silicon layer (Si layer)(14) stacked in this order on a silicon substrate (10). The carbon content and thickness of the Si 1-y C y layer acting as a channel layer of the MISFET are such that said Si 1-y C y layer is under tensile strain whereby the conduction and valence bands thereof are split. Therefore, charge carriers having a smaller effective mass, which have been induced by an electric field applied to an insulated gate electrode (15,16), are confined in the Si 1-y C y layer, and move in the channel direction. Furthermore, if the silicon layer containing carbon is made of Si 1-x-y Ge x C y , a structure suitable for a high-performance CMOS device can be formed. Alternatively, the silicon layers may contain a slight amount of carbon or germanium, and a Schottky gate may be provided whereby a MESFET is achieved.

    摘要翻译： 具有非常高的迁移率，包括第一硅层（Si层）层叠在这方面的一个MISFET（12），硅层包含碳（SI 1-YÇy层）（13）和任选的，第二硅层（Si层）（14） 订购一个硅衬底（10）上。 所述Si 1-YÇy层作用的作为MISFET的沟道层中的碳含量和厚度都在寻求即所述Si 1-YÇy层处于拉伸应变，由此导带和价带其被分割。 因此，充电具有较小有效质量，其具有在应用被诱导通过电场对绝缘栅电极（15,16）在所述Si 1-YÇy层被限制的载体，并在通道方向上移动。 进一步，如果包含碳的硅层是Si 1-X-yGexCy，适于高性能CMOS器件的结构可以形成。 可替换地，硅层可以含有碳或锗的轻微量，并且可以提供一种肖特基栅极由此MESFET实现。

    MOS transistor and its fabrication method
    6.
    发明公开
    MOS transistor and its fabrication method 审中-公开
    MOS晶体管和Verfahren zu dessen Herstellung

    公开(公告)号：EP1274134A3

    公开(公告)日：2006-11-02

    申请号：EP02014863.1

    申请日：2002-07-04

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Takagi, Takeshi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66651 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78639

    摘要： A semiconductor device comprises an Si substrate, an isolation insulating film formed on the Si substrate, an Si layer formed on the Si substrate, a gate oxide film formed on the Si layer, a gate electrode formed on the gate oxide film, a sidewall formed on the side face of the gate electrode, a gate silicide film formed on the gate electrode, source and drain regions formed at both the sides of the gate electrode and including a part of the Si layer, and a silicide film formed on the source and drain regions. Because the source and drain regions are formed on a layer-insulating film so as to be overlayed, it is possible to decrease the active region and cell area of a device. Thereby, a high-speed operation and high integration can be realized.

    摘要翻译： 半导体器件包括Si衬底，形成在Si衬底上的隔离绝缘膜，形成在Si衬底上的Si层，形成在Si层上的栅极氧化膜，形成在栅氧化膜上的栅电极，形成侧壁 在栅电极的侧面上，形成在栅电极上的栅极硅化物膜，形成在栅电极的两侧的源极和漏极区，并且包括一部分Si层，以及形成在源极上的硅化物膜 排水区。 由于源极和漏极区域形成在层间绝缘膜上以便被覆盖，所以可以减小器件的有源区域和单元面积。 由此，能够实现高速运转，高集成度。

    Semiconductor device and manufacturing method of the same
    9.
    发明公开
    Semiconductor device and manufacturing method of the same 有权
    Halbleiterbauelement undzugehörigesHerstellungsverfahren

    公开(公告)号：EP1229584A2

    公开(公告)日：2002-08-07

    申请号：EP02002649.8

    申请日：2002-02-05

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Ohnishi, Teruhito ,  Takagi, Takeshi ,  Asai, Akira ,  Fujii, Taizo ,  Sugiura, Mitsuo ,  Minami, Yoshihisa

    IPC分类号： H01L27/08

    CPC分类号： H01L29/93 ,  H01L27/0664 ,  H01L27/0808

    摘要： A variable capacitor includes an N + layer including a variable capacitance region, a P + layer epitaxially grown on the N + layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N + layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P + layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N + layer, reduction in variation range of the capacitance can be suppressed.

    摘要翻译： 可变电容器包括包含可变电容区域的N +层，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层 的可变电容器。 由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。

    Heterojunction bipolar transistor and method for fabricating the same
    10.
    发明公开
    Heterojunction bipolar transistor and method for fabricating the same 审中-公开
    Heteroübergang-Bipolartransistor和Verfahren zur Herstellung

    公开(公告)号：EP1037284A2

    公开(公告)日：2000-09-20

    申请号：EP00105401.4

    申请日：2000-03-14

    申请人： Matsushita Electric Industrial Co., Ltd.

    发明人： Asai, Akira ,  Oonishi,Teruhito ,  Takagi, Takeshi ,  Saitoh, Tohru ,  Hara, Yoshihiro ,  Yuki, Koichiro ,  Nozawa, Katsuya ,  Kanzawa, Yoshihiko ,  Katayama, Koji ,  Ichikawa, Yo

    IPC分类号： H01L29/737 ,  H01L21/331 ,  H01L27/06 ,  H01L21/8249

    CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

    摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

    摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电器开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体衬底的一部分上形成作为外部基底的第二导电类型的半导体层，而在半导体衬底中形成与外部基底相同的导电类型的接点防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。