公开(公告)号：EP1037284A3

公开(公告)日：2002-10-30

申请号：EP00105401.4

申请日：2000-03-14

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Asai, Akira ,  Oonishi,Teruhito ,  Takagi, Takeshi ,  Saitoh, Tohru ,  Hara, Yoshihiro ,  Yuki, Koichiro ,  Nozawa, Katsuya ,  Kanzawa, Yoshihiko ,  Katayama, Koji ,  Ichikawa, Yo

IPC分类号： H01L29/737 ,  H01L21/331 ,  H01L27/06 ,  H01L21/8249

CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer (102) of a first conductivity type is formed in a region of a semiconductor substrate (100) sandwiched by device isolation. A collector opening (110) is formed through a first insulating layer (108) deposited on the semiconductor substrate (100) so that the range of the collector opening (110) covers the collector layer (102) and part of the device isolation. A semiconductor layer of a second conductivity type (111) as an external base is formed on a portion of the semiconductor substrate located inside the collector opening (110), while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

公开(公告)号：EP1229584A2

公开(公告)日：2002-08-07

申请号：EP02002649.8

申请日：2002-02-05

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Ohnishi, Teruhito ,  Takagi, Takeshi ,  Asai, Akira ,  Fujii, Taizo ,  Sugiura, Mitsuo ,  Minami, Yoshihisa

IPC分类号： H01L27/08

CPC分类号： H01L29/93 ,  H01L27/0664 ,  H01L27/0808

摘要： A variable capacitor includes an N + layer including a variable capacitance region, a P + layer epitaxially grown on the N + layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N + layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P + layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N + layer, reduction in variation range of the capacitance can be suppressed.

摘要翻译： 可变电容器包括包含可变电容区域的N +层，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层 的可变电容器。 由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。

公开(公告)号：EP1037284A2

公开(公告)日：2000-09-20

申请号：EP00105401.4

申请日：2000-03-14

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Asai, Akira ,  Oonishi,Teruhito ,  Takagi, Takeshi ,  Saitoh, Tohru ,  Hara, Yoshihiro ,  Yuki, Koichiro ,  Nozawa, Katsuya ,  Kanzawa, Yoshihiko ,  Katayama, Koji ,  Ichikawa, Yo

IPC分类号： H01L29/737 ,  H01L21/331 ,  H01L27/06 ,  H01L21/8249

CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电器开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体衬底的一部分上形成作为外部基底的第二导电类型的半导体层，而在半导体衬底中形成与外部基底相同的导电类型的接点防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

公开(公告)号：EP1020900A3

公开(公告)日：2000-09-20

申请号：EP00100592.5

申请日：2000-01-12

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Yuki, Koichiro ,  Saitoh, Tohru ,  Kubo, Minoru ,  Ohnaka, Kiyoshi ,  Asai, Akira ,  Katayama, Koji

IPC分类号： H01L29/165 ,  H01L29/167 ,  H01L21/04 ,  H01L21/265

CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167

摘要： An Si 1-y Ge y layer (where 0 1-y Ge y layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the Si 1-y Ge y layer can be suppressed. As a result, the Si/Si 1-y Ge y interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.

摘要翻译： 在半导体衬底上依次形成Si 1-yGey层（其中0

公开(公告)号：EP1229584A3

公开(公告)日：2004-10-27

申请号：EP02002649.8

申请日：2002-02-05

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Ohnishi, Teruhito ,  Takagi, Takeshi ,  Asai, Akira ,  Fujii, Taizo ,  Sugiura, Mitsuo ,  Minami, Yoshihisa

IPC分类号： H01L27/08 ,  H01L27/06 ,  H01L21/8249 ,  H01L21/822 ,  H01L29/93 ,  H01L29/737

CPC分类号： H01L29/93 ,  H01L27/0664 ,  H01L27/0808

摘要： A variable capacitor includes an N + layer including a variable capacitance region, a P + layer epitaxially grown on the N + layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N + layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P + layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N + layer, reduction in variation range of the capacitance can be suppressed.

公开(公告)号：EP1710842B1

公开(公告)日：2008-11-12

申请号：EP06012402.1

申请日：2000-03-14

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Asai, Akira ,  Oonishi, Teruhito ,  Takagi, Takeshi ,  Saitho, Tohru, Matsushita Elec. Ind. Co., Ltd. ,  Hara, Yoshihiro ,  Yuki, Koichiro, c/o Matsushita Elec.Ind. Co., Ltd. ,  Nozawa, Katsuya ,  Kanzawa, Yoshihiko, Matsushita El. Ind. Co.,Ltd. ,  Katayama, Koji ,  Ichikawa, Yo

IPC分类号： H01L29/737 ,  H01L21/331 ,  H01L27/06 ,  H01L21/8249

CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

公开(公告)号：EP1710842A1

公开(公告)日：2006-10-11

申请号：EP06012402.1

申请日：2000-03-14

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Asai, Akira ,  Oonishi, Teruhito ,  Takagi, Takeshi ,  Saitho, Tohru ,  Hara, Yoshihiro ,  Yuki, Koichiro ,  Nozawa, Katsuya ,  Kanzawa, Yoshihiko ,  Katayama, Koji ,  Ichikawa, Yo

IPC分类号： H01L29/737 ,  H01L21/331 ,  H01L27/06 ,  H01L21/8249

CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电器开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体衬底的一部分上形成作为外部基底的第二导电类型的半导体层，而在半导体衬底中形成与外部基底相同的导电类型的接点防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

公开(公告)号：EP1351282A3

公开(公告)日：2004-07-28

申请号：EP03007306.8

申请日：2003-03-31

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Notake, Hidenori ,  Ohnishi, Teruhito ,  Asai, Akira ,  Aoki, Shigetaka

IPC分类号： H01L21/306 ,  H01L21/20 ,  H01L21/205 ,  C23C16/44

CPC分类号： H01L21/0209 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/32134 ,  H01L29/66242

摘要： Immediately after a Si/SiGe film containing a contaminant is formed over all surfaces of a substrate by epitaxial growth, a portion of the Si/SiGe film formed to the back surface side of the substrate is removed by wet etching. In addition, the Si/SiGe film is subjected to processing with heating in a container, after which a dummy run is carried out in the container. These processings prevent secondary wafer contamination through a stage, a robot arm or a vacuum wand for handling a wafer and the contamination of the container also used in the fabrication process of a semiconductor device free from any group IV element but Si.

公开(公告)号：EP1020900A2

公开(公告)日：2000-07-19

申请号：EP00100592.5

申请日：2000-01-12

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Yuki, Koichiro ,  Saitoh, Tohru ,  Kubo, Minoru ,  Ohnaka, Kiyoshi ,  Asai, Akira ,  Katayama, Koji

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/04 ,  H01L29/12

CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167

摘要： An Si 1-y Ge y layer (where 0 1-y Ge y layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the Si 1-y Ge y layer can be suppressed. As a result, the Si/Si 1-y Ge y interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.

摘要翻译： 在半导体衬底上依次形成Si1-yGey层（其中0

公开(公告)号：EP1605076A9

公开(公告)日：2007-02-21

申请号：EP05018537.0

申请日：2003-03-31

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Notake, Hidenori ,  Ohnishi, Teruhito ,  Asai, Akira ,  Aoki, Shigetaka

IPC分类号： H01L21/306 ,  H01L21/20 ,  H01L21/205 ,  C23C16/44

CPC分类号： H01L21/0209 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/32134 ,  H01L29/66242

摘要： Immediately after a Si/SiGe film containing a contaminant is formed over all surfaces of a substrate by epitaxial growth, a portion of the Si/SiGe film formed to the back surface side of the substrate is removed by wet etching. In addition, the Si/SiGe film is subjected to processing with heating in a container, after which a dummy run is carried out in the container. These processings prevent secondary wafer contamination through a stage, a robot arm or a vacuum wand for handling a wafer and the contamination of the container also used in the fabrication process of a semiconductor device free from any group IV element but Si.