PROGRAMMABLE CONDUCTOR RANDOM ACCESS MEMORY AND METHOD FOR SENSING SAME
    1.
    发明授权
    PROGRAMMABLE CONDUCTOR RANDOM ACCESS MEMORY AND METHOD FOR SENSING SAME 有权
    随着对他的阅读可编程梯子和方式直接存取存储器

    公开(公告)号:EP1476877B1

    公开(公告)日:2008-05-21

    申请号:EP03742713.5

    申请日:2003-02-10

    IPC分类号: G11C11/34 H01L45/00

    摘要: A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).

    A PROGRAMMABLE CONDUCTOR RANDOM ACCESS MEMORY AND A METHOD FOR WRITING THERETO
    3.
    发明公开
    A PROGRAMMABLE CONDUCTOR RANDOM ACCESS MEMORY AND A METHOD FOR WRITING THERETO 有权
    与可编程梯子和相关的编程进程内存随机访问

    公开(公告)号:EP1456851A1

    公开(公告)日:2004-09-15

    申请号:EP02799242.9

    申请日:2002-12-16

    发明人: HUSH, Glen

    IPC分类号: G11C11/34 G11C7/12

    摘要: The present invention provides an improved write circuit and method for writing a programmable conductor random access memory (PCRAM) cell. The method comprises precharging a bit line to a first voltage and applying a second voltage to a first terminal of a chalcogenide memory element. A second terminal of the chalcogenide memory element is selectively coupled to the bit line to produce a voltage across the memory element sufficient to write a predetermined resistance state into the element. The first voltage may take on two different values to program two different resistance states into the memory element.

    PROGRAMMABLE CONDUCTOR RANDOM ACCESS MEMORY AND METHOD FOR SENSING SAME
    4.
    发明公开
    PROGRAMMABLE CONDUCTOR RANDOM ACCESS MEMORY AND METHOD FOR SENSING SAME 有权
    随着对他的阅读可编程梯子和方式直接存取存储器

    公开(公告)号:EP1476877A1

    公开(公告)日:2004-11-17

    申请号:EP03742713.5

    申请日:2003-02-10

    IPC分类号: G11C11/34 H01L45/00

    摘要: A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).

    A PROGRAMMABLE CONDUCTOR RANDOM ACCESS MEMORY AND A METHOD FOR WRITING THERETO
    6.
    发明授权
    A PROGRAMMABLE CONDUCTOR RANDOM ACCESS MEMORY AND A METHOD FOR WRITING THERETO 有权
    与可编程梯子和相关的编程进程内存随机访问

    公开(公告)号:EP1456851B1

    公开(公告)日:2009-11-04

    申请号:EP02799242.9

    申请日:2002-12-16

    发明人: HUSH, Glen

    IPC分类号: G11C11/34 G11C7/12

    摘要: The present invention provides an improved write circuit and method for writing a programmable conductor random access memory (PCRAM) cell. The method comprises precharging a bit line to a first voltage and applying a second voltage to a first terminal of a chalcogenide memory element. A second terminal of the chalcogenide memory element is selectively coupled to the bit line to produce a voltage across the memory element sufficient to write a predetermined resistance state into the element. The first voltage may take on two different values to program two different resistance states into the memory element.