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22 条记录 (耗时 0.012 秒)

    PROGRAMMABLE CONDUCTOR RANDOM ACCESS MEMORY AND METHOD FOR SENSING SAME
    2.
    发明授权
    PROGRAMMABLE CONDUCTOR RANDOM ACCESS MEMORY AND METHOD FOR SENSING SAME 有权
    随着对他的阅读可编程梯子和方式直接存取存储器

    公开(公告)号：EP1476877B1

    公开(公告)日：2008-05-21

    申请号：EP03742713.5

    申请日：2003-02-10

    申请人： Micron Technology, Inc.

    发明人： CASPER, Stephen, L. ,  DUESMAN, Kevin, G. ,  HUSH, Glen

    IPC分类号： G11C11/34 ,  H01L45/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/79

    摘要： A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).

    SENSE AMPLIFIER CIRCUIT WITH TWO CURRENT PATHS AND A CAPACITOR
    4.
    发明公开
    SENSE AMPLIFIER CIRCUIT WITH TWO CURRENT PATHS AND A CAPACITOR 审中-公开
    具有两个电流路径和电容器的感测放大器电路

    公开(公告)号：EP3309788A1

    公开(公告)日：2018-04-18

    申请号：EP17181975.8

    申请日：2017-07-18

    申请人： NXP USA, Inc.

    发明人： SADD, Michael A. ,  CHOY, John Scott ,  NEAVES, Michael Garrett

    IPC分类号： G11C7/06 ,  G11C13/00 ,  G11C11/16

    CPC分类号： G11C11/1673 ,  G11C7/06 ,  G11C7/062 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1693 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0057

    摘要： In one embodiment, a sense amplifier circuit includes two current paths. Each path includes a transistor configured as a current source during a memory read operation and a second transistor. During the first phase of a memory read operation, the first current path is coupled to one cell and the second current path is coupled to a second cell. The sense amplifier circuit includes a capacitor that during a first phase of a memory read operation, is coupled between two corresponding nodes of the two paths to store a voltage difference between the two nodes. During the second phase, the cell/current path couplings are swapped and the capacitor is coupled to the control terminal of one of the second transistors to control the conductivity of the transistor for adjusting a voltage of an output node to indicate the value of the data being read.

    摘要翻译： 在一个实施例中，读出放大器电路包括两个电流路径。 每个路径包括在存储器读取操作期间被配置为电流源的晶体管和第二晶体管。 在存储器读取操作的第一阶段期间，第一电流路径耦合到一个单元并且第二电流路径耦合到第二单元。 读出放大器电路包括电容器，该电容器在存储器读取操作的第一阶段期间耦合在两个路径的两个对应节点之间以存储两个节点之间的电压差。 在第二阶段期间，单元/电流路径耦合被交换，并且电容器被耦合到第二晶体管之一的控制端子以控制晶体管的电导率以调整输出节点的电压以指示数据的值 正在阅读。

    MEMRISTIVE COMPUTATION OF A VECTOR CROSS PRODUCT
    7.
    发明公开
    MEMRISTIVE COMPUTATION OF A VECTOR CROSS PRODUCT 审中-公开
    一种矢量交叉产品的令人信服的计算

    公开(公告)号：EP3261091A1

    公开(公告)日：2017-12-27

    申请号：EP17177270.0

    申请日：2017-06-22

    申请人： Hewlett Packard Enterprise Development LP

    发明人： MERCED GRAFALS, Emmanuelle J. ,  DAVILA MELENDEZ, Noraica ,  STRACHAN, John Paul

    IPC分类号： G11C13/00

    CPC分类号： G06F17/16 ,  G11C7/1006 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2213/77

    摘要： Memristive computation of a cross product is disclosed. One example is a crossbar array of memory elements that include a number of column lines perpendicular to a number of row lines, a memory element located at each intersection of a row line and a column line. A programming voltage is applied at each memory element to change a resistance value to represent a respective entry in a skew symmetric matrix representing a first vector, and an input voltage is applied along each row line to represent a dimensional component of a second vector. Sensors located at each column line measure output voltages along column lines, where the output voltages are generated by applying input voltages received by memory elements located along the row line to resistance values of the respective memory elements. Differential amplifiers collate the output voltages for pairs of sensors to generate dimensional components of the cross product.

    摘要翻译： 披露了交叉产品的记忆计算。 一个例子是存储器元件的交叉列阵列，其包括与多个行线垂直的多个列线，位于行线和列线的每个交叉点处的存储器元件。 在每个存储器元件处施加编程电压以改变电阻值以表示代表第一矢量的斜对称矩阵中的相应条目，并且沿每条行线施加输入电压以表示第二矢量的维度分量。 位于每条列线处的传感器测量沿着列线的输出电压，其中通过将沿着行线的存储元件接收的输入电压施加到各个存储元件的电阻值来产生输出电压。 差分放大器对传感器对的输出电压进行比较，以生成叉积的尺寸分量。

    DDR COMPATIBLE MEMORY CIRCUIT ARCHITECTURE FOR RESISTIVE CHANGE ELEMENT ARRAYS
    8.
    发明公开
    DDR COMPATIBLE MEMORY CIRCUIT ARCHITECTURE FOR RESISTIVE CHANGE ELEMENT ARRAYS 审中-公开
    DDR-VERTRÄGLICHEARCHITEKTUR EINER SPEICHERSCHALTUNGFÜRRESISTIVE WECHSELELEMENTARRAYS

    公开(公告)号：EP3125249A1

    公开(公告)日：2017-02-01

    申请号：EP16181948.7

    申请日：2016-07-29

    申请人： Nantero, Inc.

    发明人： BERTIN, Claude L. ,  ROSENDALE, Glen

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0069 ,  B82Y10/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/025 ,  G11C23/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2213/35 ,  G11C2213/82 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/1778 ,  H03K19/17796 ,  Y10S977/94

    摘要： A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.

    摘要翻译： 公开了一种用于电阻变化元件阵列的高速存储器电路架构。 一组电阻变化元件组织成行和列，每列由字线和每行由两个位线提供服务。 每行电阻变化元件包括一对参考元件和读出放大器。 参考元件是在对应于SET条件的电阻和对应于阵列中使用的电阻变化元件内的RESET条件的电阻之间具有电阻值的电阻元件。 通过将一行的位线之一通过由字线选择的电阻变化元件放电并同时对行的位线中的另一个通过参考元件进行放电，并比较两条线上的放电速率来执行高速读操作 使用行的读出放大器。 存储状态数据作为高速同步数据脉冲发送到输出数据总线。 从外部同步数据总线接收高速数据，并通过存储器阵列配置中的电阻变化元件内的PROGRAM操作存储高速数据。