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1.发明授权
公开(公告)号：EP1476877B1
公开(公告)日：2008-05-21
申请号：EP03742713.5
申请日：2003-02-10
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C2013/0042 , G11C2013/0054 , G11C2013/009 , G11C2213/79
摘要： A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).
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2.发明授权
公开(公告)号：EP0861503B1
公开(公告)日：2002-02-27
申请号：EP96939640.7
申请日：1996-11-13
IPC分类号： H01L23/522 , H01L27/02
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for increasing the number of contacts provided between two conductive layers separated by an insulator in a semiconductor integrated circuit chip is disclosed. In a first row of contacts, each contact (314) in the row is separated by a distance, L. A second row of contacts is formed parallel to the first row. Each contact (310, 312) in the second row is spaced a distance of L from other contacts in the row. However, the second row is staggered from the first row, such that each contact is halfway between adjacent contacts in the first row. Each contact in the second row is located a distance of L from the two closest contacts in the first row. Successive rows are formed in similar staggered manner.
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公开(公告)号：EP0928484A1
公开(公告)日：1999-07-14
申请号：EP97910822.0
申请日：1997-10-07
摘要： A detection circuit for detecting unblown and blown conditions for an anti-fuse. The detection circuit includes a precharge circuit for applying a precharge to the anti-fuse during a precharge time interval, and a sampling circuit for coupling the anti-fuse to the detection node to provide a voltage at the detection node that is indicative of the ability of the anti-fuse to retain a charge during the discharge time interval. An output circuit that is coupled to the detection node is responsive to the voltage provided at the detection node to provide a first output for indicating an unblown condition for the anti-fuse and a second output for indicating a blown condition for the anti-fuse.
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公开(公告)号：EP1540655B1
公开(公告)日：2019-07-03
申请号：EP03791803.4
申请日：2003-08-26
IPC分类号： G11C7/12 , G11C11/4094 , G11C7/06 , G11C11/4091
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5.发明公开SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION DURING EXTENDED REFRESH PERIODS OF DYNAMIC RANDOM ACCESS MEMORY DEVICES 有权系统和方法减少电力使用过程中延长了刷新周期的动态随机存取存储器块
公开(公告)号：EP1828716A1
公开(公告)日：2007-09-05
申请号：EP05852054.5
申请日：2005-11-22
发明人： CASPER, Stephen, L.
IPC分类号： G01C7/00
CPC分类号： G11C11/406 , G11C7/1006 , G11C7/1078 , G11C11/40615 , G11C11/4074 , G11C11/4096 , G11C2211/4067 , G11C2211/4068
摘要： A dynamic random access memory ('DRAM') device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode and in the static refresh mode when memory cells are being refreshed. In between refresh bursts in the static refresh mode, the cell plate voltage selector couples a reduced voltage to the cell plate. This reduces the voltage across diode junctions formed between the source/drain of respective access transistor and the substrate. The reduced voltage reduces the discharge current flowing from memory cells capacitors, thereby allowing a reduction in the required refresh rate and a consequential reduction in power consumption.
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公开(公告)号：EP0864176B1
公开(公告)日：2002-02-13
申请号：EP96942060.3
申请日：1996-11-25
IPC分类号： H01L27/02
CPC分类号： H01L27/0288
摘要： An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.
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7.发明授权SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION DURING EXTENDED REFRESH PERIODS OF DYNAMIC RANDOM ACCESS MEMORY DEVICES 有权系统和方法减少电力使用过程中延长了刷新周期的动态随机存取存储器块
公开(公告)号：EP1828716B1
公开(公告)日：2011-05-04
申请号：EP05852054.5
申请日：2005-11-22
发明人： CASPER, Stephen, L.
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1006 , G11C7/1078 , G11C11/40615 , G11C11/4074 , G11C11/4096 , G11C2211/4067 , G11C2211/4068
摘要： A dynamic random access memory ('DRAM') device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode and in the static refresh mode when memory cells are being refreshed. In between refresh bursts in the static refresh mode, the cell plate voltage selector couples a reduced voltage to the cell plate. This reduces the voltage across diode junctions formed between the source/drain of respective access transistor and the substrate. The reduced voltage reduces the discharge current flowing from memory cells capacitors, thereby allowing a reduction in the required refresh rate and a consequential reduction in power consumption.
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公开(公告)号：EP0929899B1
公开(公告)日：2003-09-10
申请号：EP97945513.6
申请日：1997-10-03
CPC分类号： G11C17/18
摘要： An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.
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公开(公告)号：EP0929899A1
公开(公告)日：1999-07-21
申请号：EP97945513.0
申请日：1997-10-03
CPC分类号： G11C17/18
摘要： An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.
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公开(公告)号：EP0861503A1
公开(公告)日：1998-09-02
申请号：EP96939640.0
申请日：1996-11-13
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for increasing the number of contacts provided between two conductive layers separated by an insulator in a semiconductor integrated circuit chip is disclosed. In a first row of contacts, each contact (314) in the row is separated by a distance, L. A second row of contacts is formed parallel to the first row. Each contact (310, 312) in the second row is spaced a distance of L from other contacts in the row. However, the second row is staggered from the first row, such that each contact is halfway between adjacent contacts in the first row. Each contact in the second row is located a distance of L from the two closest contacts in the first row. Successive rows are formed in similar staggered manner.
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