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    LIDDED SEMICONDUCTOR PACKAGE
    2.
    发明公开
    LIDDED SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：EP3993022A1

    公开(公告)日：2022-05-04

    申请号：EP21203120.7

    申请日：2021-10-18

    Applicant: MEDIATEK Inc.

    Inventor： CHIU, Shih-Chao ,  CHEN, Chi-Yuan ,  HSU, Wen-Sung ,  HSIEH, Ya-Jui ,  HSU, Yao-Pang ,  HUANG, Wen-Chun

    IPC: H01L23/00 ,  H01L23/10 ,  H01L23/36 ,  H01L23/40 ,  H01L23/473

    Abstract: A semiconductor package (1) includes a substrate (100) having a top surface (100a) and a bottom surface (100b); a semiconductor die (110) mounted on the top surface (100a) of the substrate (100); and a two-part lid (300) mounted on a perimeter of the top surface (100a) of the substrate (100) and housing the semiconductor die (110). The lid (300) comprises an annular lid base (310) and a cover plate (320) removably installed on the annular lid base (310). The semiconductor package (1) can be uncovered by removing the cover plate (320) and a forced cooling module can be installed in place of the cover plate (320).

    SEMICONDUCTOR PACKAGE HAVING RE-DISTRIBUTION LAYER STRUCTURE ON SUBSTRATE COMPONENT
    3.
    发明公开
    SEMICONDUCTOR PACKAGE HAVING RE-DISTRIBUTION LAYER STRUCTURE ON SUBSTRATE COMPONENT 审中-公开

    公开(公告)号：EP3848962A2

    公开(公告)日：2021-07-14

    申请号：EP20213349.2

    申请日：2020-12-11

    Applicant: MEDIATEK INC.

    Inventor： TSAI, Yi-Lin ,  CHIU, Shih-Chao ,  HSU, Wen-Sung ,  CHIU, Sang-Mao ,  CHEN, Chi-Yuan ,  HSU, Yao-Pang

    IPC: H01L23/498 ,  H01L23/538

    Abstract: A semiconductor package (40) includes a substrate component (100) having a first surface (Si), a second surface (S 2 ) opposite to the first surface (S 1 ), and a sidewall surface (SW) extending between the first surface (Si) and the second surface (S 2 ); a re-distribution layer, RDL, structure (130) disposed on the first surface (Si) and electrically connected to the first surface (Si) through first connecting elements (112) comprising solder bumps or balls; a plurality of ball grid array, BGA, balls (110) mounted on the second surface (S 2 ) of the substrate component (100); and at least one integrated circuit die (300) mounted on the RDL structure (130) through second connecting elements (310).

    ANTENNA-IN-MODULE PACKAGE-ON-PACKAGE WITH AIR TRENCHES
    4.
    发明公开
    ANTENNA-IN-MODULE PACKAGE-ON-PACKAGE WITH AIR TRENCHES 审中-公开

    公开(公告)号：EP4250476A1

    公开(公告)日：2023-09-27

    申请号：EP23160705.2

    申请日：2023-03-08

    Applicant: MediaTek Inc.

    Inventor： HSIEH, Ya-Jui ,  CHEN, Chi-Yuan ,  CHIU, Shih-Chao ,  HSU, Yao-Pang

    IPC: H01Q1/22 ,  H01Q21/08

    Abstract: An antenna-in-module package-on-package (1) includes an antenna package (20) having a top surface (S1) and a bottom surface (S2) opposing the top surface (S1). The antenna package (20) includes a radiative antenna element (40) on the bottom surface (S2). A chip package (10) is mounted on the top surface (S1) of the antenna package (20). The chip package (10) includes a semiconductor chip (101). Conductive elements (SB) are disposed between the antenna package (20) and the chip package (10) to electrically interconnect the chip package (10) and the antenna package (20). The radiative antenna element (40) is disposed on the bottom surface (S2) of the antenna package (20). At least one air trench (CT1 - CT3) is disposed on the bottom surface (S2) of the antenna package (20).

    SEMICONDUCTOR PACKAGE WITH A HEAT SINK BONDED TO A SEMICONDUCTOR CHIP WITH A BONDING LAYER AND TO A MOLDING MATERIAL WITH A THERMAL INTERFACE MATERIAL
    5.
    发明公开
    SEMICONDUCTOR PACKAGE WITH A HEAT SINK BONDED TO A SEMICONDUCTOR CHIP WITH A BONDING LAYER AND TO A MOLDING MATERIAL WITH A THERMAL INTERFACE MATERIAL 审中-公开

    公开(公告)号：EP3751603A3

    公开(公告)日：2021-01-06

    申请号：EP20179156.3

    申请日：2020-06-10

    Applicant: MediaTek Inc

    Inventor： HSIEH, Ya-Jui ,  HSU, Chia-Hao ,  CHEN, Tai-Yu ,  HSU, Yao-Pang

    IPC: H01L23/367 ,  H01L23/31 ,  H01L23/36 ,  H01L23/373 ,  H01L23/42

    Abstract: A semiconductor package structure (200, 300, 400) includes a substrate (102), a semiconductor die (106), a molding material (108), a first bonding layer (126), and a thermal interface material (120). The semiconductor die (106) is disposed over the substrate (102). The molding material (108) surrounds the semiconductor die (106). The first bonding layer (126) is disposed over the semiconductor die (106). The thermal interface material (120) is disposed over the molding material (108). The semiconductor package structure (200, 300, 400) may further comprise a heatsink (122) disposed over the bonding layer (126), wherein the thermal interface material (120) may connect the molding material (108) and the heatsink (122). The inclusion of both of thermal interface material (120) and the bonding layer (126) improves the heat dissipation efficiency without increasing stress, which is preferred for high-power applications, resulting at the same time in enhancement of thermal performance, manufacturability and reliability. The thermal interface material (120) may be adhesive. The thermal interface material (120) may surround the first bonding layer (126). A metal layer (124) may be disposed between the first bonding layer (126) and the semiconductor die (106). The thermal interface material (120) may partially surround the metal layer (124) and the bonding layer (126). The thermal interface material (120) may be spaced apart from the metal layer (124) and the bonding layer (126) by a gap, to prevent the issues caused by different coefficients of thermal expansion (CTE) of the thermal interface material (120), the metal layer (124) and the bonding layer (126). The thermal interface material (120) may be thicker than the metal layer (124) and thicker than the bonding layer (126). The thermal interface material (120) may have a notch and/or may be cut off by a gap (132) or by a plurality of gaps, to release gas generated during the manufacturing process. The semiconductor package structure (200, 300, 400) may further comprise a conductive element (104) (e.g., conductive ball structures, conductive pillar structures or conductive paste structures) disposed between the semiconductor die (106) and the substrate (102). The semiconductor package structure (400) may further comprise another heatsink (130) disposed below the substrate (102) and bonded onto the substrate (102) through a second bonding layer (128), wherein the first bonding layer (126) has a melting point lower than the second bonding layer (128). The first bonding layer (126) may comprise SnBi, SnBiAg, or a combination thereof. A sidewall of the thermal interface material (120) may be aligned with a sidewall of the molding layer (108) or inside it. The upper surface of the semiconductor die (106) may be covered or exposed by the molding material (108).

    SEMICONDUCTOR PACKAGE HAVING RE-DISTRIBUTION LAYER STRUCTURE ON SUBSTRATE COMPONENT
    6.
    发明公开
    SEMICONDUCTOR PACKAGE HAVING RE-DISTRIBUTION LAYER STRUCTURE ON SUBSTRATE COMPONENT 审中-公开

    公开(公告)号：EP3848962A3

    公开(公告)日：2021-08-25

    申请号：EP20213349.2

    申请日：2020-12-11

    Applicant: MEDIATEK INC.

    Inventor： TSAI, Yi-Lin ,  CHIU, Shih-Chao ,  HSU, Wen-Sung ,  CHIU, Sang-Mao ,  CHEN, Chi-Yuan ,  HSU, Yao-Pang

    IPC: H01L23/498 ,  H01L23/538

    Abstract: A semiconductor package (40) includes a substrate component (100) having a first surface (Si), a second surface (S 2 ) opposite to the first surface (S 1 ), and a sidewall surface (SW) extending between the first surface (Si) and the second surface (S 2 ); a re-distribution layer, RDL, structure (130) disposed on the first surface (Si) and electrically connected to the first surface (Si) through first connecting elements (112) comprising solder bumps or balls; a plurality of ball grid array, BGA, balls (110) mounted on the second surface (S 2 ) of the substrate component (100); and at least one integrated circuit die (300) mounted on the RDL structure (130) through second connecting elements (310).

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