公开(公告)号：EP4376067A3

公开(公告)日：2024-09-04

申请号：EP24168496.8

申请日：2020-03-12

申请人： MediaTek Inc.

发明人： LIN, Tzu-Hung ,  LIU, Yuan-Chin

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31

CPC分类号： H01L25/0655 ,  H01L23/66 ,  H01L2224/1210520130101 ,  H01L2924/1515120130101 ,  H01L2924/1531120130101 ,  H01L2924/1816220130101 ,  H01L2224/1622720130101 ,  H01L2224/7320420130101 ,  H01L2224/3222520130101 ,  H01L2224/9212520130101 ,  H01L2924/35120130101 ,  H01L2924/351120130101 ,  H01L2924/351220130101 ,  H01L2224/4813720130101 ,  H01L2224/7327720130101 ,  H01L2223/667720130101 ,  H01L2224/0410520130101 ,  H01L2223/668820130101 ,  H01L24/20 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/49822 ,  H01L23/562 ,  H01L23/3128

摘要： A semiconductor package structure (500, 700b) is provided. The semiconductor package structure (500, 700b) includes a substrate, a first semiconductor die (115a), and a second semiconductor die (115b). The substrate includes a first substrate partition (502a) and a second substrate partition (502b). The first substrate partition (502a) has a first wiring structure. The second substrate partition (502b) is adjacent to the first substrate partition (502a) and has a second wiring structure. The first substrate partition (502a) and the second substrate partition (502b) are surrounded by a first molding material (504). The first semiconductor die (115a) is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die (115b) is disposed over the substrate and electrically coupled to the second wiring structure. The semiconductor package structure (500b) further comprises a frame (113) surrounding the first substrate (502a) and the second substrate (502b), wherein the frame (113) is surrounded by the first molding material (504).

公开(公告)号：EP4406391A1

公开(公告)日：2024-07-31

申请号：EP22777135.9

申请日：2022-08-23

申请人： QUALCOMM INCORPORATED

发明人： DUTTA, Ranadeep ,  KIM, Jonghae ,  LAN, Je-Hsiung

IPC分类号： H10N99/00

CPC分类号： H01L28/90 ,  H01L28/82 ,  H01L23/642 ,  H01L23/49822 ,  H01L2224/0826520130101 ,  H01L2224/1626520130101 ,  H01L25/16 ,  H01L2924/1531120130101 ,  H01L2924/1904120130101 ,  H01L2924/1910420130101 ,  H01L2924/1910320130101 ,  H01G4/40 ,  H01L23/5385 ,  H01L23/49816 ,  H01L24/08 ,  H01L2224/8089620130101 ,  H01L2224/8089520130101 ,  H01L24/16 ,  H01G4/33 ,  H01G4/012 ,  H01G4/005 ,  H01G4/008 ,  H01G4/1272

公开(公告)号：EP4386836A1

公开(公告)日：2024-06-19

申请号：EP23164715.7

申请日：2023-03-28

申请人： NXP USA, Inc.

发明人： Gong, Zhiwei ,  Acar, Mustafa ,  Zhou, Tingdong ,  Wenzel, Robert Joseph

IPC分类号： H01L23/538

CPC分类号： H01L23/5385 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/50 ,  H01G4/00 ,  H01L28/60 ,  H01L28/10

摘要： An interposer may include one or more passive components integrated within a dielectric substrate and may include one or more three-dimensional (3D) connectors that surround respective portions of the dielectric substrate. Component terminals of the one or more passive components may each be disposed on the same side of the interposer. For example, the interposer may be disposed between a first package and a second package, such that the connectors of the interposer electrically connect the first package to the second package. The component terminals of the one or more passive components may couple the integrated passive components of the interposer to only one package to which the interposer is coupled.

公开(公告)号：EP4372811A1

公开(公告)日：2024-05-22

申请号：EP22207783.6

申请日：2022-11-16

申请人： AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

发明人： Oggioni, Stefano Sergio

IPC分类号： H01L23/498 ,  H01L23/60

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/60

摘要： A component carrier (100) which comprises a stack (102) comprising at least two electrically insulating layer structures (106, 106', 106") and at least one electrically conductive layer structure (104, 104', 104"), a plurality of wiring elements (108) provided in one of the at least two electrically insulating layer structures (106), said plurality of wiring elements (108) being arranged in a wiring plane (162) to form a first row (110) of equidistant wiring elements (108) arranged along a straight direction within the wiring plane (162), and a second row (112) of equidistant wiring elements (108) arranged along the straight direction within the wiring plane (162), a plurality of further wiring elements (108') provided in another of the at least two electrically insulating layer structures (106'), wherein the at least one electrically conductive layer structure (104, 104', 104") comprises several conductive areas (111) being electrically insulated with respect to each other, each of said conductive areas (111) being connected to at least one of the plurality of wiring elements (108) and to at least one of the plurality of further wiring elements (108'), and wherein each of the conductive areas (111) of the at least one electrically conductive layer structure (104, 104', 104") is spaced by a distance (d) from a respective conductive area (111) connected to an adjacent wiring element (108, 108'), wherein said distance (d) is at least 5% of a diameter (D1) of the wiring element (108, 108').

公开(公告)号：EP3709344B1

公开(公告)日：2024-05-08

申请号：EP20162559.7

申请日：2020-03-12

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/66 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L25/0655 ,  H01L23/66 ,  H01L2224/1210520130101 ,  H01L2924/1515120130101 ,  H01L2924/1531120130101 ,  H01L2924/1816220130101 ,  H01L2224/1622720130101 ,  H01L2224/7320420130101 ,  H01L2224/3222520130101 ,  H01L2224/9212520130101 ,  H01L2924/35120130101 ,  H01L2924/351120130101 ,  H01L2924/351220130101 ,  H01L2224/4813720130101 ,  H01L2224/7327720130101 ,  H01L2223/667720130101 ,  H01L2224/0410520130101 ,  H01L2223/668820130101 ,  H01L24/20 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/49822 ,  H01L23/562 ,  H01L23/3128

公开(公告)号：EP3384529A1

公开(公告)日：2018-10-10

申请号：EP16870090.4

申请日：2016-11-30

申请人： At&S (China) Co., Ltd.

发明人： TUOMINEN, Mikael

IPC分类号： H01L25/065 ,  H01L23/552

CPC分类号： H01L23/492 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2225/06524 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/3025

摘要： An electronic device includes first and second component carrier packages having respective embedded electronic components and at least one respective external terminal. The second component carrier package is mounted on the first component carrier package by electrically and mechanically connecting the at least one respective external terminals. The first component carrier package further includes an electromagnetic radiation shielding structure formed as an electrically conductive coating and being configured for at least partially shielding electromagnetic radiation from propagating between an exterior and an interior of the first component carrier package.

公开(公告)号：EP3381050A1

公开(公告)日：2018-10-03

申请号：EP16806380.8

申请日：2016-11-17

申请人： Medtronic, Inc.

发明人： DAY, John K. ,  RUBEN, David A. ,  SANDLIN, Michael S.

IPC分类号： H01L23/15 ,  H01L23/498

CPC分类号： H05K1/0306 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/16225 ,  H05K1/09 ,  H05K1/115 ,  H05K1/144 ,  H05K3/10 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4611 ,  H05K3/4644 ,  H05K2201/09036

摘要： A device having embedded metallic structures in a glass is provided. The device includes a first wafer, at least one conductive trace, a planarized insulation layer and a second wafer. The first wafer has at least one first wafer via that is filled with conductive material. The at least one conductive trace is formed on the first wafer. The at least one conductive trace is in contact with the at least one first wafer via that is filled with the conductive material. The planarized insulation layer is formed over the first wafer and at least one conductive trace. The planarized insulation layer further has at least one insulation layer via that provides a path to a portion of the at least one conductive trace. The second wafer is bonded to the planarized insulation layer.

公开(公告)号：EP2596531B1

公开(公告)日：2018-10-03

申请号：EP11749029.2

申请日：2011-07-18

申请人： Marvell World Trade Ltd.

发明人： SUTARDJA, Sehat ,  WU, Albert ,  WU, Scott

IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L25/50 ,  H01L23/12 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the present disclosure provide a method that comprises providing a first die having a surface comprising a bond pad to route electrical signals of the first die and attaching the first die to a layer of a substrate. The method further comprises forming one or more additional layers of the substrate to embed the first die in the substrate and coupling a second die to the one or more additional layers, the second die having a surface comprising a bond pad to route electrical signals of the second die. The second die is coupled to the one or more additional layers such that electrical signals are routed between the first die and the second die.

公开(公告)号：EP3361841A1

公开(公告)日：2018-08-15

申请号：EP16853478.2

申请日：2016-09-29

申请人： Hitachi Metals, Ltd.

发明人： MASUKAWA, Junichi ,  IKEDA, Hatsuo

IPC分类号： H05K3/46 ,  H01L23/12

CPC分类号： H01L21/4857 ,  B32B18/00 ,  B32B37/06 ,  B32B37/10 ,  B32B38/10 ,  B32B2315/02 ,  B32B2457/00 ,  H01L21/486 ,  H01L23/12 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/46

摘要： A method of prducing a multi-layer ceramic substrate includes the steps of: (A) preparing a first ceramic green sheet with a thermal expansion layer arranged thereon, and at least one second ceramic green sheet with no thermal expansion layer arranged thereon; (B) laminating the first and second ceramic green sheets with the thermal expansion layer sandwiched therebetween, thereby obtaining a green sheet laminate; (C) pressure-bonding together the ceramic green sheets of the green sheet laminate; (D) heating and thereby expanding the thermal expansion layer in the pressure-bonded green sheet laminate; (E) extracting a portion of the green sheet laminate that has been displaced by the expansion of the thermal expansion layer, thereby forming a cavity in the green sheet laminate; and (F) sintering the green sheet laminate with the cavity formed therein.

公开(公告)号：EP3350832A1

公开(公告)日：2018-07-25

申请号：EP16756829.4

申请日：2016-07-29

申请人： Qualcomm Incorporated

发明人： LAN, Je-Hsiung Jeffrey ,  MUDAKATTE, Niranjan Sunil ,  YUN, Changhan Hobie ,  KIM, Daeik Daniel ,  ZUO, Chengjie ,  BERDY, David Francis ,  VELEZ, Mario Francisco ,  KIM, Jonghae

IPC分类号： H01L23/522

CPC分类号： H01L27/01 ,  H01L21/4846 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L28/10 ,  H01L28/75 ,  H01L2224/11

摘要： A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.