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1.发明授权2-PHASE GAIN CALIBRATION AND SCALING SCHEME FOR SWITCHED CAPACITOR SIGMA-DELTA MODULATOR USING A CHOPPER VOLTAGE REFERENCE 有权采用斩波参考电压的开关电容Σ-Δ调制器的两阶段增益校准和标定方案
公开(公告)号：EP2591555B1
公开(公告)日：2018-03-07
申请号：EP11700774.0
申请日：2011-01-11
CPC分类号： H03M1/0663 , H03M1/0665 , H03M3/422 , H03M3/456 , H03M3/464
摘要： A sigma-delta modulator has a chopper voltage reference providing a reference signal having a clock dependent offset voltage, a single-bit or a multi-bit digital-to-analog converter (DAC); a plurality of capacitor pairs; a plurality of switches to couple any capacitor pair to an input or reference signal; and a control unit controlling sampling through said switches to perform a charge transfer in two phases wherein any capacitor pair can be selected to be assigned to the input or reference signal, wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically, and wherein a DAC output value and a reference offset state define switching sequences wherein each switching sequence independently rotates said capacitor pairs and wherein at least one switching sequence is selected depending on a current DAC output value and a current reference offset state.
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公开(公告)号：EP3075076B1
公开(公告)日：2019-09-04
申请号：EP14819176.0
申请日：2014-11-26
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3.发明公开CONFIGURING MULTI-BIT SLAVE ADDRESSING ON A SERIAL BUS USING A SINGLE EXTERNAL CONNECTION 审中-公开SETTING多位从属寻址与EINZELAUSSEANSCHLUSS的串行总线
公开(公告)号：EP2176774A1
公开(公告)日：2010-04-21
申请号：EP08782367.0
申请日：2008-07-25
IPC分类号： G06F13/42
CPC分类号： G06F13/4072
摘要： Unique addresses for a plurality of devices may be programmed through a single external connection (pin) on each device by using a one of a plurality of different analog voltage or current values on the single external pin in combination with a serial clock of a serial data bus for each device requiring a unique binary address. The unique binary address is stored in the device after detection of certain number of clocks on the serial data bus. Once the unique binary address has been stored in the device, the single external connection may be used for another purpose such as a multifunction external connection. This unique binary address may be retained by the device until a power-on-reset (POR) or general reset condition occurs. Address detection and address load commands on the serial bus may also perform the same address definition and storage functions.
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公开(公告)号：EP3075076A1
公开(公告)日：2016-10-05
申请号：EP14819176.0
申请日：2014-11-26
摘要： A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator.
摘要翻译： 时钟振荡器包括产生高速时钟信号并包括数字调整功能的高速振荡器; 一个在时钟输入端接收所述高速时钟信号的计数器; 具有低漂移并控制所述计数器的时基，其中所述计数器产生参考值和计数器值之间的差值; 以及数字积分器，接收所述差值并提供所述高速振荡器的调整数据。
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5.发明公开2-PHASE GAIN CALIBRATION AND SCALING SCHEME FOR SWITCHED CAPACITOR SIGMA-DELTA MODULATOR USING A CHOPPER VOLTAGE REFERENCE 有权两相和VERSTÄRKUNGSKALIBRIER-SKALIERSCHEMA为Σ-Δ调制器交换机使用电容的斩波参考电压
公开(公告)号：EP2591555A1
公开(公告)日：2013-05-15
申请号：EP11700774.0
申请日：2011-01-11
CPC分类号： H03M1/0663 , H03M1/0665 , H03M3/422 , H03M3/456 , H03M3/464
摘要： A sigma-delta modulator has a chopper voltage reference providing a reference signal having a clock dependent offset voltage, a single-bit or a multi-bit digital-to-analog converter (DAC); a plurality of capacitor pairs; a plurality of switches to couple any capacitor pair to an input or reference signal; and a control unit controlling sampling through said switches to perform a charge transfer in two phases wherein any capacitor pair can be selected to be assigned to the input or reference signal, wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically, and wherein a DAC output value and a reference offset state define switching sequences wherein each switching sequence independently rotates said capacitor pairs and wherein at least one switching sequence is selected depending on a current DAC output value and a current reference offset state.
摘要翻译： Σ-Δ调制器具有提供具有时钟相关的偏移电压的参考信号的斩波电压基准，一个单比特或多比特数字 - 模拟转换器（DAC）; 电容器对一个多元化; 开关耦合任何电容器对在输入或参考信号的多元性; 并通过所述控制单元，控制取样开关以执行worin任何电容器对可被选择为被分配给输入或参考信号中的两个相的电荷转移，电荷的多元性后worin传送的增益误差消除执行通过旋转 电容器对周期性，和worin一个DAC的输出值和基准偏移状态限定worin每个切换序列unabhängig旋转并且所述电容器对和worin至少一个开关序列被选择取决于电流DAC输出值和当前基准偏置状态切换序列。
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