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公开(公告)号：EP2306460A2
公开(公告)日：2011-04-06
申请号：EP11000145.0
申请日：2006-09-29
发明人： Kim, Jin-Ki , Pyeon, Hong Beom
IPC分类号： G11C11/4193 , G11C11/4197 , G11C16/06
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0688 , G06F13/4243 , G11C5/066 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C8/10 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2207/107 , G11C2216/30
摘要： An apparatus, system, and method for controlling data transfer between a serial data link interface and memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple serial data links and multiple memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.
摘要翻译： 公开了一种用于控制半导体存储器中的串行数据链路接口和存储体之间的数据传输的装置，系统和方法。 在一个示例中，公开了具有多个串行数据链路的闪存器件和多个存储器组，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。
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公开(公告)号：EP2490225A1
公开(公告)日：2012-08-22
申请号：EP12168362.7
申请日：2008-02-06
发明人： Kim, Jin-Ki , Pyeon, Hong Beom
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/10
摘要： A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory ceils in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell.
摘要翻译： 一种用于对NAND快闪单元进行编程以最小化程序应力同时允许随机页面编程操作的方法。 该方法包括在位线从NAND串行解耦时，从正偏置的源极线非对称地预充电NAND串，然后将编程电压施加到选中的存储器单元，然后施加位线数据。 在非对称预充电和施加编程电压之后，所有选定的存储单元将被设置为编程禁止状态，因为它们将从其各自的NAND串中的其他存储器单元解耦，并且它们的通道将被局部地升压到电压有效 用于禁止编程。 VSS偏置位线将本地升压通道放电至VSS，从而允许对所选存储单元进行编程。 VDD偏置的位线将对预充电的NAND串没有影响，由此保持所选存储器单元的编程禁止状态。
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3.发明公开Modular command structure for memory and memory system 审中-公开Modulare Befehlsstrukturfüreinen Speicher und Speichersystem
公开(公告)号：EP2487794A2
公开(公告)日：2012-08-15
申请号：EP12158821.4
申请日：2007-08-20
发明人： Kim, Jin-Ki , Oh, HakJune , Pyeon, Hong Beom
CPC分类号： G06F3/0629 , G06F3/0604 , G06F3/0673 , G06F13/4243 , G06F13/4256 , G11C7/10 , G11C7/1042 , G11C7/20 , G11C8/06 , G11C8/10 , Y02D10/14 , Y02D10/151
摘要： A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.
摘要翻译： 包括存储器系统和存储器控制器的系统连接到主机系统。 存储器系统具有存储数据的至少一个存储器件。 控制器将来自主机系统的请求转换成由至少一个存储设备可解释的一个或多个可分离命令。 每个命令具有模块化结构，其包括用于至少一个存储器设备之一的地址标识符和表示要由所述至少一个存储器设备之一执行的操作的命令标识符。 至少一个存储器设备和控制器处于用于通信的串联连接配置中，使得只有一个存储器设备与控制器通信以输入到存储器系统中。 存储器系统可以包括连接到公共总线的多个存储器件。
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公开(公告)号：EP1981030A1
公开(公告)日：2008-10-15
申请号：EP08006223.5
申请日：2006-09-29
发明人： Pyeon, Hong Beom , Kim, Jin-Ki , Oh, HakJune
CPC分类号： G11C7/10 , G06F12/0623 , G06F13/4247 , G06F13/4256 , G11C5/066 , G11C16/06
摘要： A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs of a second device later in the daisy chain to accommodate the transfer of information, such as data, address and command information, and control signals to the second device from the first device. The devices coupled in the daisy chain comprise a serial input (SI) and a serial output (SO). Information is input to a device via the SI. The information is output from the device via the SO. The SO of an earlier device is the daisy chain cascade is coupled to the SI of a device later in the daisy chain cascade. Information input to the earlier device via the device's SI. is passed through the device and output from the device via the device's SO. The information is then transferred to the later device's s SI via the connection from the earlier device's SO and the later device' SI.
摘要翻译： 用于串联菊花链级联装置的技术。 设备以菊花链级联布置耦合，使得第一设备的输出耦合到菊链中的第二设备的输入，以适应诸如数据，地址和命令信息的信息以及控制信号到 第二设备从第一设备。 耦合在菊花链中的装置包括串行输入（SI）和串行输出（SO）。 信息通过SI输入到设备。 信息通过SO从设备输出。 较早的器件的SO是菊花链级联耦合到菊花链级联以后的器件的SI。 通过设备的SI输入到早期设备的信息。 通过设备并通过设备的SO从设备输出。 然后，信息通过早期设备的SO和后期设备的SI的连接传输到后期设备的SI。
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公开(公告)号：EP2251872B1
公开(公告)日：2014-04-09
申请号：EP09001914.2
申请日：2009-02-11
发明人： Pyeon, Hong Beom
CPC分类号： G11C5/00 , G06F12/06 , G06F13/1684 , G06F2212/1032 , G06F2212/2022 , G11C7/22 , G11C8/12
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6.发明公开Apparatus and method of page program operation for memory devices connected in series 审中-公开设备和方法，用于被连接在彼此串联的存储器设备的页编程操作
公开(公告)号：EP2662860A1
公开(公告)日：2013-11-13
申请号：EP13179743.3
申请日：2008-02-13
发明人： Pyeon, Hong Beom , Kim, Jin-Ki , Oh, HakJune
CPC分类号： G06F13/4243 , G06F13/4247
摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.
摘要翻译： 提供了一种装置和页编程操作的方法。 当执行页面编程操作与所选择的存储器设备，存储器控制器将数据装载到因此到另一个选定的存储设备的，以便在页缓冲区中的一个选定的存储设备和页缓冲器，用于存储所述数据的一个备份拷贝 ， 在事件所做的数据未被成功编程到所选择的一个存储装置的存储器单元，那么所述存储器控制器从所述其他存储器设备的页缓冲器中恢复的数据。 由于数据的副本被存储在其他存储器设备的页缓冲器中，存储器控制器不需要向本地数据存储在其数据存储元件。
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公开(公告)号：EP2306460A3
公开(公告)日：2011-07-27
申请号：EP11000145.0
申请日：2006-09-29
发明人： Kim, Jin-Ki , Pyeon, Hong Beom
IPC分类号： G11C11/4193 , G11C11/4197 , G11C16/06
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0688 , G06F13/4243 , G11C5/066 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C8/10 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2207/107 , G11C2216/30
摘要： An apparatus, system, and method for controlling data transfer between a serial data link interface and memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple serial data links and multiple memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.
摘要翻译： 公开了一种用于控制半导体存储器中的串行数据链路接口与存储体之间的数据传输的装置，系统和方法。 在一个示例中，公开了具有多个串行数据链路和多个存储体的闪存设备，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 另外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。
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8.发明公开Selective broadcasting of data in series connected devices 有权SelektiveDatenfunkübertragung在reihengeschalteten Vorrichtungen
公开(公告)号：EP2251872A1
公开(公告)日：2010-11-17
申请号：EP09001914.2
申请日：2009-02-11
发明人： Pyeon, Hong Beom
CPC分类号： G11C5/00 , G06F12/06 , G06F13/1684 , G06F2212/1032 , G06F2212/2022 , G11C7/22 , G11C8/12
摘要： A method and system for the selective broadcasting of commands to a subset of a plurality of devices connected in series to a memory controller, where each of the plurality of devices has a unique identification number (ID). The memory controller designates the subset of devices to execute the command, excluding the non-selected devices from executing the command. The memory controller encodes the ID numbers of the designated devices into a single coded address, and sends the command along with the coded address in a packet to the series connected devices. Each device receives the packet in a serial bitstream and decodes the coded address using its ID number in order to determine whether it is selected or not. If the device is selected, the command is executed. Otherwise, the packet is forwarded without executing the command.
摘要翻译： 一种用于将命令选择性地广播到与存储器控制器串联连接的多个设备的子集的方法和系统，其中多个设备中的每一个具有唯一的标识号（ID）。 存储器控制器指定要执行命令的设备的子集，排除未被选择的设备执行命令。 存储器控制器将指定设备的ID号编码为单个编码地址，并将该命令与编码地址一起发送到串联连接的设备。 每个设备以串行比特流接收分组，并使用其ID号对编码的地址进行解码，以便确定是否被选择。 如果选择了该设备，则执行该命令。 否则，不执行命令就转发报文。
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公开(公告)号：EP1981032B1
公开(公告)日：2013-02-06
申请号：EP08006225.0
申请日：2006-09-29
发明人： Pyeon, Hong Beom , Kim, Jin-Ki , Oh, HakJune
CPC分类号： G11C7/10 , G06F12/0623 , G06F13/4247 , G06F13/4256 , G11C5/066 , G11C16/06
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公开(公告)号：EP1981030B1
公开(公告)日：2012-09-12
申请号：EP08006223.5
申请日：2006-09-29
发明人： Pyeon, Hong Beom , Kim, Jin-Ki , Oh, HakJune
CPC分类号： G11C7/10 , G06F12/0623 , G06F13/4247 , G06F13/4256 , G11C5/066 , G11C16/06
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