公开(公告)号：EP3382710A1

公开(公告)日：2018-10-03

申请号：EP18172012.9

申请日：2011-08-10

申请人： Micron Technology, Inc.

发明人： GRUNZKE, Terry

IPC分类号： G11C7/10 ,  G11C8/06 ,  H04L25/02 ,  G06F13/40 ,  G11C5/00 ,  G06F12/00 ,  G06F13/16 ,  G11C7/20 ,  G11C7/22 ,  G11C16/06 ,  G11C16/00 ,  G06F12/06

CPC分类号： G06F12/0653 ,  G06F12/0661 ,  G06F13/16 ,  G06F13/18 ,  G11C5/00 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/06 ,  H04L25/0278 ,  H04L25/0298 ,  Y02D10/14

摘要： A method of operating a memory system (300) comprising a plurality of memory devices (310-316), the method comprising:
loading respective sets of termination information to a subset of memory devices (310, 312, 314 and/or 316) of the plurality of memory devices (310-316);
wherein, for each memory device of the subset of memory devices (310, 312, 314 and/or 316), its respective set of termination information comprises address information of the memory system (300) and one or more termination values associated with that address information.

公开(公告)号：EP3175459A4

公开(公告)日：2017-11-01

申请号：EP14898561

申请日：2014-07-30

申请人： HEWLETT-PACKARD DEV COMPANY L P

发明人： NG BOON BING ,  WIN THIDA MA ,  GE NING ,  RANDO JOSE JEHROME

IPC分类号： G11C16/02 ,  B41J2/175 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08 ,  G11C19/00 ,  G11C19/28

CPC分类号： G11C16/06 ,  B41J2/17546 ,  G11C8/12 ,  G11C16/08 ,  G11C19/00 ,  G11C19/28

摘要： A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

公开(公告)号：EP2920787B1

公开(公告)日：2017-09-27

申请号：EP13783743.1

申请日：2013-10-09

申请人： Silicon Storage Technology Inc.

发明人： TRAN, Hieu, Van ,  NGUYEN, Hung, Quoc ,  REITEN, Mark

IPC分类号： G11C7/04 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  G11C29/02 ,  G11C5/02 ,  G11C5/06 ,  G11C16/30 ,  G11C29/26 ,  G11C29/00 ,  G11C16/34 ,  G11C29/12 ,  H01L25/065 ,  H01L25/18 ,  G11C16/08 ,  G11C16/10

CPC分类号： G11C29/76 ,  G11C5/02 ,  G11C5/06 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/26 ,  G11C2213/71 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

摘要： A three-dimensional flash memory system is disclosed.

公开(公告)号：EP2979269A4

公开(公告)日：2016-11-16

申请号：EP13880644

申请日：2013-03-27

申请人： HEWLETT PACKARD ENTPR DEV LP

发明人： BUCHANAN BRENT EDGAR

IPC分类号： G11C13/00 ,  H03K19/173

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C16/06 ,  G11C16/30 ,  G11C2013/0073 ,  G11C2013/0088 ,  G11C2213/75 ,  H03K19/1733

公开(公告)号：EP2839463B1

公开(公告)日：2016-11-02

申请号：EP13717699.6

申请日：2013-04-15

申请人： SanDisk Technologies LLC

发明人： COSTA, Xiying ,  LI, Haibo ,  HIGASHITANI, Masaaki ,  MUI, Man, L.

IPC分类号： G11C16/14 ,  G11C5/02 ,  H01L27/115 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34

CPC分类号： G11C16/14 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3445 ,  G11C16/3472 ,  H01L27/1157 ,  H01L27/11582

公开(公告)号：EP3057100A1

公开(公告)日：2016-08-17

申请号：EP15168965.0

申请日：2015-05-22

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Chang, Kuen-Long ,  Chen, Ken-Hui ,  Hsieh, Ming-Chih

IPC分类号： G11C7/10 ,  G11C16/06 ,  G06F12/02

CPC分类号： G11C7/00 ,  G06F12/0246 ,  G11C7/1015 ,  G11C7/1045 ,  G11C16/06

摘要： A memory device includes a memory array and a logic unit communicatively coupled to the memory array. The memory array includes a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The logic unit is configured to receive a read instruction, and perform a read operation in a first access mode or in a second access mode. In the first access mode, the logic unit sequentially reads out the array data stored in the plurality of pages. In the second access mode, the logic unit sequentially reads out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.

摘要翻译： 存储器件包括存储器阵列和通信地耦合到存储器阵列的逻辑单元。 存储器阵列包括用于存储阵列数据的多个页面和分别对应于用于存储额外数据的多个页面的多个额外阵列。 逻辑单元被配置为接收读取指令，并且以第一访问模式或第二访问模式执行读取操作。 在第一访问模式中，逻辑单元顺序地读出存储在多个页面中的阵列数据。 在第二访问模式中，逻辑单元顺序地读出存储在多个页面中的阵列数据和存储在多个额外阵列中的额外数据。

公开(公告)号：EP2532005A4

公开(公告)日：2016-06-22

申请号：EP11740503

申请日：2011-02-07

申请人： ZENO SEMICONDUCTOR INC

发明人： WIDJAJA YUNIARTO ,  OR-BACH ZVI

IPC分类号： G11C11/34 ,  G11C11/404 ,  H01L27/108 ,  H01L29/78

CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C11/565 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/06 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/788 ,  H01L29/7881

摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

公开(公告)号：EP2715729A4

公开(公告)日：2015-10-07

申请号：EP12792360

申请日：2012-05-24

申请人： MICRON TECHNOLOGY INC

发明人： ERDMANN MICHAEL A ,  LUNZER KEITH J ,  JEDDELOH JOSEPH M

IPC分类号： G11C7/10 ,  G06F3/06 ,  G06F13/14 ,  G06F13/38 ,  G11C16/06 ,  G11C16/34

CPC分类号： G06F3/0659 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0661 ,  G06F3/067 ,  G06F3/0688 ,  G06F13/385 ,  G11C16/06 ,  G11C16/349 ,  Y02D10/14 ,  Y02D10/151

摘要： Memory system controllers can include a host bus adapter (HBA) and a serial advanced technology attachment (SA) programming compliant device coupled to the HBA via a function-specific interconnect configured to simultaneously transfer a command, a response, and other information between the HBA and the SA programming compliant device.

摘要翻译： 存储器系统控制器可以包括主机总线适配器（HBA）和通过功能专用互连耦合到HBA的串行高级技术附件（SA）编程兼容设备，其被配置为在HBA之间同时传送命令，响应和其他信息 和SA编程兼容设备。

公开(公告)号：EP2923357A2

公开(公告)日：2015-09-30

申请号：EP14701667.9

申请日：2014-01-14

申请人： Silicon Storage Technology Inc.

发明人： TRAN, Hieu, Van ,  LY, Anh ,  VU, Thuan ,  NGUYEN, Hung, Quoc

IPC分类号： G11C5/14 ,  G11C16/12 ,  G11C16/30 ,  H02M3/07

CPC分类号： G11C16/06 ,  G11C5/145 ,  G11C16/12 ,  G11C16/30 ,  H02M3/07 ,  H02M3/073

摘要： A hybrid charge pump and control circuit for use in a memory device is disclosed.

摘要翻译： 一种混合电荷泵和控制电路，用于使用在存储装置中是游离缺失盘。

公开(公告)号：EP2891069A1

公开(公告)日：2015-07-08

申请号：EP12883648.3

申请日：2012-08-28

申请人： Hewlett-Packard Development Company, L.P.

发明人： LI, Sheng ,  YOON, Doe Hyun ,  JOUPPI, Norman Paul

IPC分类号： G06F13/14 ,  G11C16/06

CPC分类号： G06F3/0619 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/1471 ,  G06F12/0891 ,  G06F2003/0691 ,  G06F2212/1032 ,  G06F2212/202 ,  G06F2212/222 ,  G06F2212/251 ,  G06F2212/304 ,  G11C16/06

摘要： A method of performing data transactions in a high performance persistent memory comprising, with a processor, updating data by writing new data to non-volatile memory (NVM) and receiving a done signal from a transaction accelerator communicatively coupled to the NVM. An apparatus for high performance persistent memory, comprising a processor, a memory controller communicatively coupled to the processor, and non-volatile memory communicatively coupled to the memory controller and processor, the non-volatile memory comprising an ACID transaction accelerator, in which the processor updates data on the non-volatile memory (NVM) by writing new data to the NVM, and receives a done signal from the an ACID transaction accelerator when the data has been updated.