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公开(公告)号：EP4016126A1
公开(公告)日：2022-06-22
申请号：EP21209523.6
申请日：2021-11-22
申请人： NXP USA, Inc.
IPC分类号： G01S13/42 , G01S13/34 , G01S13/931 , G01S7/35
摘要： A radar system utilizing a linear chirp that can achieve a larger MIMO virtual array than traditional systems is provided. Transmit channels transmit distinct chirp signals in an overlapped fashion such that the pulse repetition interval is kept short and the frame is kept short. This alleviates range migration and aids in achieving a high frame update rate. The chirp signals from differing transmitters can be separated on receive in the range spectrum domain, such that a MIMO virtual array construction is possible. Distinct chirps are delayed versions of the first chirp signal. Chirps overlap in the fast-time domain, but due to delay, there is separation in the range spectrum domain. When the delay is at least the instrument round-trip delay, transmitters are separable. Further, the wavelengths are identical across transmitters such that there is no residual-range versus angle ambiguity issue present in the claimed frequency-offset modulation range division MIMO system.
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2.发明公开
公开(公告)号：EP3567720A1
公开(公告)日：2019-11-13
申请号：EP19166889.6
申请日：2019-04-02
申请人： NXP USA, Inc.
摘要： A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a common-mode reference voltage generation circuit uses one or more additional sampling switched capacitors to selectively couple the first and second reference voltages to the amplifier input during the gain phase when the input voltage is between the high and low threshold voltages using a switching configuration of switches that are controllable to connect the sampling switched capacitors to the one or more central nodes in the sampling phase, and to connect the amplifier output in feedback to the input sampling circuit in the gain phase while simultaneously connecting the one or more central nodes to the first amplifier input.
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公开(公告)号：EP3570436A1
公开(公告)日：2019-11-20
申请号：EP19174769.0
申请日：2019-05-15
申请人： NXP USA, Inc.
摘要： A switched-capacitor gain stage circuit (70) and method include an amplifier (71) connected to an input sampling circuit (73) with sampling switched capacitors (C1, C2) for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes (72) to an amplifier input during a gain phase, wherein a reference loading circuit uses a plurality of sampling switched capacitors (C3, C4) connected in a switching configuration to selectively couple a first reference voltage and/or a second reference voltage to the central node by pre-charging the plurality of sampling switched capacitors with the first and second reference voltages during the sampling phase, and by coupling each of the first and second reference voltages to at least one of the plurality of sampling switched capacitors when connected to the central node during the gain phase.
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4.发明公开
公开(公告)号：EP3835809A1
公开(公告)日：2021-06-16
申请号：EP20208040.4
申请日：2020-11-17
申请人： NXP USA, Inc.
IPC分类号： G01S7/02 , G01S13/34 , G01S13/87 , G01S13/931 , G01S13/58
摘要： A radar system, apparatus, architecture, and method are provided for generating a transmit reference or chirp signal that is applied to a waveform generator having a frequency offset generator and a plurality of single channel modulation mixers configured to generate a plurality of transmit signals having different frequency offsets from the transmit reference signal for encoding and transmission as N radio frequency encoded transmit signals which are reflected from a target and received at a receive antenna as a target return signal that is down-converted to an intermediate frequency signal and converted by a highspeed analog-to-digital converter to a digital signal that is processed by a radar control processing unit which performs fast time processing steps to generate a range spectrum comprising N segments which correspond, respectively, to the N radio frequency encoded transmit signals transmitted over the N transmit antennas.
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5.发明公开
公开(公告)号：EP3835810A1
公开(公告)日：2021-06-16
申请号：EP20207899.4
申请日：2020-11-16
申请人： NXP USA, Inc.
摘要： A radar system, apparatus, architecture, and method are provided for generating a transmit reference or chirp signal to produce a plurality of transmit signals having different frequency offsets from the transmit reference signal for encoding and transmission as N radio frequency encoded transmit signals which are reflected from a target and received at a receive antenna as a target return signal that is downconverted to an intermediate frequency signal and converted by a high-speed analog-to-digital converter to a digital signal that is processed by a radar control processing unit which performs fast time processing steps to generate a range spectrum comprising N segments which correspond, respectively, to the N radio frequency encoded transmit signals transmitted over the N transmit antennas.
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公开(公告)号：EP3672082A1
公开(公告)日：2020-06-24
申请号：EP19210477.6
申请日：2019-11-20
申请人： NXP USA, Inc.
摘要： A method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection includes randomizing an order of a plurality of unit elements of a DAC, wherein each of the unit elements is controlled by a respective one of a plurality of digital inputs of the DAC. The plurality of digital inputs is sequentially asserted over at least a subset of a full set of the digital inputs to generate a plurality of analog values of an output of the DAC. A first SNDR of the DAC is measured from the plurality of analog values. A maximum SNDR, corresponding to an optimal order, is determined from the first SNDR and at least one previously measured SNDR. The optimal order of the unit elements of the DAC is stored in a memory to define connections between the digital inputs and the respective unit elements based on the optimal order.
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7.发明公开METHOD FOR TESTING DIFFERENTIAL ANALOG-TO-DIGITAL CONVERTER AND SYSTEM THEREFOR 审中-公开VERFAHREN ZUM TESTEN VON DIFFENENZIELLEM模拟数字万用表系统DAFÜR
公开(公告)号：EP3110008A1
公开(公告)日：2016-12-28
申请号：EP16175408.0
申请日：2016-06-21
申请人： NXP USA, Inc.
发明人： Chen, Tao , Garrity, Douglas Alan , Jin, Xiankun
CPC分类号： H03M1/109 , H03H19/004 , H03M1/12
摘要： A method and circuit for testing an analog-to-digital converter (ADC) are provided. The method comprises: coupling a single-ended output of an analog signal source to a differential input of an amplifier; coupling a differential output of the amplifier to a differential input of the ADC; alternately providing first and second test signals from the single-ended output of the analog signal source to first and second input terminals of the differential input of the amplifier; amplifying the first and second test signals to generate amplified differential signals at the differential output of the amplifier; providing the amplified differential signals to the differential input of the ADC; and determining if an output of the ADC is as expected. An offset may also be provided to the differential output of the amplifier. The method allows an ADC having a differential input to be tested using a digital-to-analog converter (DAC) having a single-ended output.
摘要翻译： 提供了一种用于测试模数转换器（ADC）的方法和电路。 该方法包括：将模拟信号源的单端输出耦合到放大器的差分输入; 将放大器的差分输出耦合到ADC的差分输入; 交替地将模拟信号源的单端输出的第一和第二测试信号提供给放大器的差分输入的第一和第二输入端; 放大第一和第二测试信号以在放大器的差分输出处产生放大的差分信号; 将放大的差分信号提供给ADC的差分输入; 并且确定ADC的输出是否如预期的那样。 还可以向放大器的差分输出提供偏移。 该方法允许使用具有单端输出的数模转换器（DAC）来测试具有差分输入的ADC。
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8.发明公开RAMP VOLTAGE GENERATOR AND METHOD FOR TESTING AN ANALOG-TO-DIGITAL CONVERTER 审中-公开VERFAHREN ZURPRÜFUNGEINES模拟数字服务器的RAMPENSPANNUNGSGENERATOR
公开(公告)号：EP3110007A1
公开(公告)日：2016-12-28
申请号：EP16175440.3
申请日：2016-06-21
申请人： NXP USA, Inc.
CPC分类号： H03K4/502 , H03M1/1071 , H03M1/109
摘要： A method and circuit for generating ramped voltages are provided. The ramp voltage generator circuit includes: a switched-capacitor amplifier having an input terminal, an output terminal, a sampling capacitor switchably coupled to the input terminal, and a gain capacitor switchably coupled to the output terminal; and a current source having a terminal coupled to a supply terminal, and a terminal coupled to the input terminal. The ramp voltage generator circuit may be coupled to test an analog-to-digital converter (ADC).
摘要翻译： 提供了一种用于产生斜坡电压的方法和电路。 斜坡电压发生器电路包括：开关电容放大器，其具有输入端子，输出端子，可切换地耦合到输入端子的采样电容器和可切换地耦合到输出端子的增益电容器; 以及电流源，其具有耦合到电源端子的端子，以及耦合到所述输入端子的端子。 斜坡电压发生器电路可以被耦合以测试模拟 - 数字转换器（ADC）。
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