公开(公告)号：EP2277211B1

公开(公告)日：2014-10-08

申请号：EP09732874.4

申请日：2009-04-15

申请人： QUALCOMM Incorporated

发明人： KANG, Seung, H. ,  LI, Xia ,  GU, Shiqun ,  NOWAK, Matthew, M.

IPC分类号： H01L43/08 ,  H01L43/12

CPC分类号： H01L43/08 ,  G11C11/161 ,  H01L43/12

公开(公告)号：EP3005562B1

公开(公告)日：2017-07-19

申请号：EP14734338.8

申请日：2014-06-02

申请人： Qualcomm Incorporated

发明人： ZUO, Chengjie ,  KIM, Jonghae ,  KIM, Daeik, D. ,  VELEZ, Mario, Francisco ,  YUN, Changhan ,  LAN, Je-Hsiung ,  MIKULKA, Robert, P. ,  NOWAK, Matthew, M.

IPC分类号： H03H7/46

CPC分类号： H03H7/463 ,  H03H3/00 ,  Y10T29/4902

公开(公告)号：EP2277211A1

公开(公告)日：2011-01-26

申请号：EP09732874.4

申请日：2009-04-15

申请人： QUALCOMM Incorporated

发明人： KANG, Seung, H. ,  LI, Xia ,  GU, Shiqun ,  NOWAK, Matthew, M.

IPC分类号： H01L43/08 ,  H01L43/12

CPC分类号： H01L43/08 ,  G11C11/161 ,  H01L43/12

摘要： A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer (36) containing an exposed first interconnect metallization, (37) a first electrode, (30) a fixed magnetization layer, (32) a tunneling barrier layer, (12) a free magnetization layer (11) and a second electrode (6). An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer (40) encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode (15) is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer (8) covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.

公开(公告)号：EP3005562A1

公开(公告)日：2016-04-13

申请号：EP14734338.8

申请日：2014-06-02

申请人： Qualcomm Incorporated

发明人： ZUO, Chengjie ,  KIM, Jonghae ,  KIM, Daeik, D. ,  VELEZ, Mario, Francisco ,  YUN, Changhan ,  LAN, Je-Hsiung ,  MIKULKA, Robert, P. ,  NOWAK, Matthew, M.

IPC分类号： H03H7/46

CPC分类号： H03H7/463 ,  H03H3/00 ,  Y10T29/4902

摘要： Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.

公开(公告)号：EP2995002A1

公开(公告)日：2016-03-16

申请号：EP14728764.3

申请日：2014-05-02

申请人： Qualcomm Incorporated

发明人： ZUO, Chengjie ,  KIM, Daeik, D. ,  LAN, Je-Hsiung ,  KIM, Jonghae ,  VELEZ, Mario, Francisco ,  YUN, Changhan ,  BERDY, David, F. ,  MIKULKA, Robert, P. ,  NOWAK, Matthew, M. ,  ZHANG, Xiangdong ,  SEE, Puay, H.

IPC分类号： H03H7/46

CPC分类号： H03H7/461 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  Y10T29/49016

摘要： Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

公开(公告)号：EP2609622A2

公开(公告)日：2013-07-03

申请号：EP11754577.2

申请日：2011-08-24

申请人： Qualcomm Incorporated

发明人： GU, Shiqun ,  NOWAK, Matthew, M. ,  SRINIVASAN, Anand

IPC分类号： H01L23/48 ,  G11C11/4076

CPC分类号： G11C11/4076 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

摘要： External memory having a high density, high latency memory block; and a low density, low latency memory block. The two memory blocks may be separately accessed by one or more processing functional units. The access may be a direct memory access, or by way of a bus or fabric switch. Through-die vias may connect the external memory to a die comprising the one or more processing functional units.

公开(公告)号：EP2286452A1

公开(公告)日：2011-02-23

申请号：EP09743273.6

申请日：2009-04-27

申请人： QUALCOMM Incorporated

发明人： KASKOUN, Kenneth ,  GU, Shiqun ,  NOWAK, Matthew, M.

IPC分类号： H01L25/065 ,  H01L23/367 ,  H01L23/373

CPC分类号： H01L25/0657 ,  H01L23/3677 ,  H01L23/3732 ,  H01L23/3735 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/01019

摘要： By filling an air gap between tiers (31,32) of a stacked IC device with a thermally conductive material (320) heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal materia can be electrically insulating. Through silicon-vias (331) can be constructe at certain locations to assist in heat dissipation away from thermally troubled locations (310).