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    Method of evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories
    1.
    发明公开
    Method of evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories 失效
    一种用于评估的非易失性EPROM，EEPROM和快闪EEPROM的存储器中的电介质层的方法。

    公开(公告)号：EP0595775A1

    公开(公告)日：1994-05-04

    申请号：EP93830134.8

    申请日：1993-04-01

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Cappelletti, Paolo Giuseppe ,  Ravazzi, Leonardo

    IPC: G11C29/00 ,  H01L21/66

    CPC classification number: G11C29/50004 ,  G06F2201/81 ,  G11C16/04 ,  G11C29/50 ,  G11C2029/5004 ,  G11C2029/5006

    Abstract: A method employing a test structure (10) identical to the memory array whose gate oxide or interpoly dielectric quality is to be determined, except for the fact that the cells are connected electrically (13-15, 17, 18, 19-21) parallel to one another. The test structure is subjected to electrical stress of such a value and polarity as to extract electrons from the floating gate of the defective-gate-oxide or defective-interpoly-dielectric cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A subthreshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide or interpoly dielectric of EPROM, EEPROM and flash-EEPROM memories.

    Abstract translation: 一种方法采用测试结构（10）相同的到所述存储器阵列，其栅氧化物或电介质间（interpoly）质量将被确定，除了在平行所述细胞电连接的factthat（13-15，17，18，19-21） 彼此。 测试结构进行求值和极性，以从有缺陷的栅氧化物或缺陷-间（interpoly）电介质单元的浮置栅提取电子并因此修改该单元的特性，同时使充电的电应力 无缺陷单元不变。 通过这种方式，只有有缺陷的单元的阈值被改变。 然后，低于阈值的电压被施加到测试结构，和通过细胞中的漏电流，所有这是关系到在结构中的至少一个有缺陷的细胞的存在，进行测量。 的电流 - 电压特性的测量和分析用于确定性采矿提供有缺陷的细胞的数目。 该方法适用于栅极氧化物或EPROM，EEPROM和快闪EEPROM存储器间介电的在线质量控制。

    Method for making twin tub integrated devices, in particular twin tub CMOS devices
    3.
    发明公开
    Method for making twin tub integrated devices, in particular twin tub CMOS devices 失效
    Methode zum Herstellen doppelwanniger integrierter Bauelemente，speziell CMOS-Bauelemente mit Zwillingswannen。

    公开(公告)号：EP0254973A1

    公开(公告)日：1988-02-03

    申请号：EP87110269.5

    申请日：1987-07-16

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Baldi, Livio ,  Cappelletti, Paolo Giuseppe

    IPC: H01L21/308 ,  H01L21/76 ,  H01L21/32

    CPC classification number: H01L21/308 ,  H01L21/033 ,  H01L21/763 ,  H01L21/82285 ,  H01L21/823892 ,  H01L27/0928 ,  Y10S148/103

    Abstract: This method for making twin tub CMOS devices with a self-aligned separation trench uses only two masking steps for forming the tubs and the trench of the CMOS, thereby saving manufacture time and lowering production costs. In particular, the trench mask is obtained by at least one masking layer deposited on the substrate and having a window at the trench region obtained in a self-aligned manner employing the tub masks which are dimensioned so as to mutually and ideally overlap at the trench region and to delimit the trench mask window.

    Abstract translation: 用于制造具有自对准分离槽的双槽CMOS器件的方法仅使用两个掩蔽步骤来形成CMOS的槽和沟槽，从而节省制造时间并降低生产成本。 特别地，沟槽掩模是通过沉积在衬底上的至少一个掩模层获得的，并且在以自对准方式获得的沟槽区域处具有窗口，该自对准方式采用盆形掩模，其尺寸被设计成相互理想地重叠在沟槽处 区域并限定沟槽掩模窗口。

    Method for ion implant programming NMOS read-only memories and NMOS read-only memory obtained thereby
    4.
    发明公开
    Method for ion implant programming NMOS read-only memories and NMOS read-only memory obtained thereby 失效
    由NMOS的离子注入编程的方法，只读存储器和一个NMOS只读存储器，从而获得。

    公开(公告)号：EP0227965A2

    公开(公告)日：1987-07-08

    申请号：EP86116625.4

    申请日：1986-11-29

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Cappelletti, Paolo Giuseppe ,  Maggioni, Franco

    IPC: H01L27/10

    CPC classification number: H01L27/112

    Abstract: The method for ion implant programing NMOS read-only memories comprises the step of increasing the concentration of boron in the channel only proximate to the source junction of the NMOS devices of the memory which are to be programed 'off'. In this manner it is possible to increase the threshold voltage of these devices without reducing the breakdown voltage thereof, so as to obtain a reliable operation of the device or memory element even for very-large-scale-integration circuits, with a reduced thickness of oxide.

    Abstract translation: 用于离子注入编程NMOS只读存储器的方法，包括在所述通道仅靠近所述存储器的NMOS器件哪些是源结增加硼的浓度的步骤，以进行编程“关闭”。 以这种方式，能够提高合成装置的阈值电压，而不会降低它们的击穿电压，以便获得可靠的操作的设备或存储元件的即使是非常大规模集成电路，具有减小的厚度 氧化物。

    Non-volatile memory with protection diode
    5.
    发明公开
    Non-volatile memory with protection diode 失效
    NichtflüchtigerSpeicher mit Schutzdiode。

    公开(公告)号：EP0614223A1

    公开(公告)日：1994-09-07

    申请号：EP93830058.9

    申请日：1993-02-17

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Cappelletti, Paolo Giuseppe

    IPC: H01L27/115 ,  H01L27/02 ,  H01L21/82

    CPC classification number: H01L27/11521 ,  G11C5/005 ,  H01L27/0255 ,  H01L27/115

    Abstract: To protect the thin tunnel oxide layer (8a) interposed between the floating gate region (6) of memory cells (1) and the substrate (2) and subject to in-process damage when the wafer is subjected to radiation, provision is made for a diode (D) connected between the control gate region (7) of the cells and the substrate (1). The diode (D) defines a conductive path which, when normal operating voltage is applied to the control gate regions (7), is turned off and has no effect on normal operation of the memory (15), and which is turned on to permit the passage of charges between the control gate region (7) and the substrate (2) when the control gate potential exceeds normal operating potential but is less than the breakdown voltage of the tunnel oxide (8a) divided by the coupling factor of the control and floating gate regions of the cells. The diode (D) is appropriately formed prior to patterning the control gate regions of the cells.

    Abstract translation: 为了保护插入在存储单元（1）的浮动栅极区域（6）和基板（2）之间的薄隧道氧化物层（8a），并且当晶片经受辐射时受到过程中的损坏，为 连接在电池的控制栅极区域（7）和基板（1）之间的二极管（D）。 二极管（D）限定了当正常工作电压施加到控制栅极区域（7）时被关闭并且对存储器（15）的正常操作没有影响并且被接通以允许 当控制栅极电位超过正常工作电位但小于隧道氧化物（8a）的击穿电压除以控制的耦合因子时，控制栅极区域（7）和衬底（2）之间的电荷通过，以及 细胞的浮栅区域。 在对单元的控制栅极区域进行构图之前，适当地形成二极管（D）。

    Method of evaluating the gate oxide of non-volatile EPROM, EEPROM and flash-EEPROM memories
    6.
    发明公开
    Method of evaluating the gate oxide of non-volatile EPROM, EEPROM and flash-EEPROM memories 失效
    Verfahren zur Bewertung des Gatteroxids nicht-flüchtigerEPROM，EEPROM和闪存EEPROM-Speicher。

    公开(公告)号：EP0594920A1

    公开(公告)日：1994-05-04

    申请号：EP92830589.5

    申请日：1992-10-29

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Cappelletti, Paolo Giuseppe ,  Ravazzi, Leonardo

    IPC: G11C29/00 ,  H01L21/66

    CPC classification number: G11C29/50004 ,  G06F2201/81 ,  G11C16/04 ,  G11C29/50 ,  G11C2029/5004 ,  G11C2029/5006

    Abstract: A method employing a test structure (10) identical to the memory array whose gate oxide quality is to be determined, except for the fact that the cells are connected electrically (13-15, 17, 18, 19-21) parallel to one another. The test structure is so stressed electrically as to extract electrons from the floating gate of the defective-gate-oxide cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A subthreshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide of EPROM, EEPROM and flash-EEPROM memories.

    Abstract translation: 使用与要确定其栅极氧化物质量的存储器阵列相同的测试结构（10）的方法，除了电池彼此平行的电连接（13-15,17,18,19-21）的事实之外 。 测试结构被电应力地从缺陷栅极 - 氧化物电池的浮动栅极提取电子，并因此改变电池的特性，同时保持无缺陷电池的电荷不变。 以这种方式，只有有缺陷的单元的阈值被改变。 然后将亚阈值电压施加到测试结构，并且测量与结构中存在至少一个有缺陷单元有关的通过单元的漏极电流。 电流 - 电压特性的测量和分析提供了确定缺陷单元的数量。 该方法适用于EPROM，EEPROM和闪存EEPROM存储器的栅氧化物的在线质量控制。

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