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18 条记录 (耗时 0.01 秒)

    Mixed typology output stage
    2.
    发明公开
    Mixed typology output stage 失效
    Ausgangstufe mit Transistoren von unterschiedlichem Typ。

    公开(公告)号：EP0657995A1

    公开(公告)日：1995-06-14

    申请号：EP93830492.0

    申请日：1993-12-07

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Cini, Carlo ,  Stefani, Fabrizio

    IPC分类号： H03F3/30

    CPC分类号： H03F3/45179 ,  H03F3/3008 ,  H03F2203/30012 ,  H03F2203/30051

    摘要： An output power stage composed of a pair of transistors driven in phase opposition and wherein the pull-up transistor is a PNP bipolar transistor and the push-down transistor is an n-channel FET has an outstandingly improved power handling capability per semiconductor area occupied, coupled with a large output voltage swing, without requiring the use of externally connected discrete boot-strap components. The "hybrid" output stage is fully complementary and the current-driven, bipolar, pull-up transistor may be driven through an auxiliary stage composed of a field effect transistor for substantially eliminating output power requisites of a signal amplification stage.

    摘要翻译： 由相位相对驱动的一对晶体管组成的输出功率级，其中上拉晶体管是PNP双极晶体管，并且下拉式晶体管是n沟道FET，每占用半导体面积的功率处理能力显着提高， 加上大的输出电压摆幅，而不需要使用外部连接的分立的引导部件。 “混合”输出级是完全互补的，并且电流驱动的双极性上拉晶体管可以通过由场效应晶体管组成的辅助级驱动，用于基本上消除信号放大级的输出功率必需品。

    Current limiter for constant current for switching driving devices
    4.
    发明公开
    Current limiter for constant current for switching driving devices 失效
    用于切换驱动装置的恒定电流的当前限制

    公开(公告)号：EP0242759A3

    公开(公告)日：1989-10-11

    申请号：EP87105439.1

    申请日：1987-04-13

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Cini, Carlo ,  Diazzi, Claudio ,  Gattavari, Giuseppe

    IPC分类号： H01H47/32 ,  H03K17/08

    CPC分类号： H01H47/325 ,  H02H3/087

    摘要： The switching driving device with current limitation, operating reliably even with high switching frequencies, comprises a drive stage (10) receiving at the input a timing clock signal (MCl) at a preset frequency and generating at the output a drive signal synchronized with the timing clock signal, a power element (11) connected at the input to the drive stage, receiving therefrom the drive signal and generating a load supply signal, a load (14) fed by the power element, and a current sensor (16,17) generating an overload signal when the current in the load has reached a preset threshold. The current limitation is obtained through a memory element (21) connected to the current sensor (16,17) and disabling the drive stage (10) in the presence of the overload signal. In order to obtain a reliable operation, in the presence of the overload signal the drive stage is controlled at a switching frequency which is lower than the preset frequency of the timing clock signal.

    A guarded electronic circuit from reversal of its supply battery polarity
    6.
    发明公开
    A guarded electronic circuit from reversal of its supply battery polarity 失效
    Gegen diePolaritätsumkehrseiner Versorgungsbatteriegeschützteelektronische Schaltung。

    公开(公告)号：EP0349836A2

    公开(公告)日：1990-01-10

    申请号：EP89111329.2

    申请日：1989-06-22

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Cini, Carlo ,  Murari, Bruno

    IPC分类号： H02H11/00

    CPC分类号： H02H11/003 ,  Y10T307/839

    摘要： A guarded electronic circuit (1) from reversal of its supply battery (2) polarity comprises a MOS power transistor (T1) connected between one pole (Vc) of the battery (2) and ground, to drive an electric load (RL) to ground, and a second, protection MOS transistor (T2) connected between the pole (Vc) and the first transistor (T1); said transistors (T1,T2), which are both provided with respective inherent diodes (D3,D4) between the source and the drain, have their related drain electrodes (D1,D2) connected together. The resulting circuit (1) is self-protected against possible reversal of the polarity of the battery to which it is connected, and can protect the electric load (RL) driven thereby.

    摘要翻译： 防止电源电路（2）反向供电电池（2）的极性包括连接在电池（2）的一极（Vc）和接地之间的MOS功率晶体管（T1），以将电负载（RL）驱动到 接地和连接在极（Vc）和第一晶体管（T1）之间的第二保护MOS晶体管（T2）; 所述晶体管（T1，T2）在源极和漏极之间均设有相应的固有二极管（D3，D4），其相关的漏电极（D1，D2）连接在一起。 所得到的电路（1）是自我保护的，以防止与其连接的电池的极性的可逆反转，并且可以保护由此驱动的电负载（RL）。

    A circuit for holding a MOS transistor in a conduction state in a voltage supply outage situation
    7.
    发明公开
    A circuit for holding a MOS transistor in a conduction state in a voltage supply outage situation 失效
    电路保持的MOS晶体管时处于导通状态的电源电压。

    公开(公告)号：EP0321702A2

    公开(公告)日：1989-06-28

    申请号：EP88119207.4

    申请日：1988-11-18

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Rossi, Domenico ,  Pietrobon, Giovanni ,  Storti, Sandro ,  Cini, Carlo

    IPC分类号： H03K17/24 ,  H03K17/06

    CPC分类号： H03K17/24 ,  H03K17/063

    摘要： A circuit (1) for holding a MOS power transistor (MP) in a conduction state on the occurrence of an outage in the voltage supply (VA), being of a type which comprises a first MOS transistor (M1) having its source (S1) connected to a line (2) of the voltage supply and its drain (D2) connected to the gate (GP) of the power transistor (MP), further comprises a diode (D) connected between the drain (D1) of the first transistor (M1) and the gate (GP) of the power transistor (MP), and a second transistor (M2) of the MOS type having its gate (G2) connected to the gate (G1) of the first transistor (M1) and its drain connected to the gate (GP) of the power transistor (MP). The circuit (1) prevents the gate capacitance (GP) of the power transistor from becoming discharged on a failure of the voltage supply (VA), thus holding that transistor in a conducting state.

    摘要翻译： 一种用于保持MOS功率晶体管（MP）（处于导通状态在所述电源电压（VA）的中断的发生，是一种类型的，它包括其源极S1的第一MOS晶体管（M1）的电路（1） ）连接至所述电压电源的线（2）和它的连接到栅极功率晶体管（MP）的（GP）漏极（D2），还包括所述第一连接的漏极（D1之间的二极管（D）） 晶体管（M1）和所述第一晶体管连接到所述栅极（G1）的栅极功率晶体管的（GP）（MP），和其栅极（G2）的MOS类型的第二晶体管（M2）（M1）和 其漏极连接到栅极的功率晶体管的（GP）（MP）。 所述电路（1）从上的电压供给（VA）的故障变得放电防止功率晶体管的栅极电容（GP），从而保持没有处于导通状态的晶体管。

    Current limiter for constant current for switching driving devices
    8.
    发明公开
    Current limiter for constant current for switching driving devices 失效
    StrombegrenzerfürKonstantstromfüreinen Treiber einesSchaltgerätes。

    公开(公告)号：EP0242759A2

    公开(公告)日：1987-10-28

    申请号：EP87105439.1

    申请日：1987-04-13

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Cini, Carlo ,  Diazzi, Claudio ,  Gattavari, Giuseppe

    IPC分类号： H01H47/32 ,  H03K17/08

    CPC分类号： H01H47/325 ,  H02H3/087

    摘要： The switching driving device with current limitation, operating reliably even with high switching frequencies, comprises a drive stage (10) receiving at the input a timing clock signal (MCl) at a preset frequency and generating at the output a drive signal synchronized with the timing clock signal, a power element (11) connected at the input to the drive stage, receiving therefrom the drive signal and generating a load supply signal, a load (14) fed by the power element, and a current sensor (16,17) generating an overload signal when the current in the load has reached a preset threshold. The current limitation is obtained through a memory element (21) connected to the current sensor (16,17) and disabling the drive stage (10) in the presence of the overload signal. In order to obtain a reliable operation, in the presence of the overload signal the drive stage is controlled at a switching frequency which is lower than the preset frequency of the timing clock signal.

    摘要翻译： 具有电流限制的开关驱动装置即使具有高开关频率也可靠地工作，包括驱动级（10），其在输入端接收预定频率的定时时钟信号（MCl），并在输出端产生与定时同步的驱动信号 时钟信号，连接到驱动级的输入端的功率元件（11），从其接收驱动信号并产生负载电源信号，由功率元件供电的负载（14）和电流传感器（16,17） 当负载中的电流达到预设阈值时产生过载信号。 通过连接到电流传感器（16,17）的存储元件（21）并且在存在过载信号的情况下禁用驱动级（10）来获得电流限制。 为了获得可靠的操作，在存在过载信号的情况下，驱动级被控制在低于定时时钟信号的预置频率的开关频率。