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26 条记录 (耗时 0.015 秒)

    SEMICONDUCTOR OPERATIONAL CIRCUIT
    2.
    发明公开
    SEMICONDUCTOR OPERATIONAL CIRCUIT 失效
    半导体工作电路

    公开(公告)号：EP0820030A1

    公开(公告)日：1998-01-21

    申请号：EP96907743.7

    申请日：1996-04-01

    申请人： SHIBATA, Tadashi ,  OHMI, Tadahiro

    发明人： SHIBATA, Tadashi ,  OHMI, Tadahiro

    IPC分类号： G06G7/12

    CPC分类号： G06G7/26

    摘要： The present invention has as an object thereof to provide a semiconductor operational circuit which is capable of instantaneously processing in parallel a large quantity of information.
    The semiconductor operational circuit of the present invention which executes a predetermined operation with respect to a first signal train of signals A 1 , A 2 , ..., A N-1 , A N (where N is a positive integer) of N signals numbered from 1 to N, and a second signal train of signals B 1 , B 2 , ..., B M-1 , B M (where M is a positive integer) of M signals numbered from 1 to M, comprising a plurality of first operational circuits for executing a predetermined operation with respect to A i and B i+n (where i is a positive integer and n is a positive or negative integer and 1 ≤ i ≤ n and 1 ≤ i + n ≤ M ) and generating an output signal C i,n , at least one second operational circuit for generating the sum S n of a part or the whole of output signals of the first operational circuits with respect to a predetermined value of n, where i has differing values, or for generating a predetermined signal T n determined by the sum S n , and a third operational circuit for finding the value of S n or T n with respect to a plurality of different n values and for determining the n value for which the maximum or minimum value of S n or T n is given.

    摘要翻译： 本发明的目的在于提供一种能够瞬时并行处理大量信息的半导体工作电路。 本发明的半导体工作电路对信号A1，A2，...，AN-1，AN（其中N是正整数）的N个信号的第一个信号序列执行预定的操作，编号从1到 N和编号从1到M的M个信号的信号B1，B2，...，BM-1，BM（其中M是正整数）的第二信号序列，包括多个第一运算电路，用于执行预定的 关于Ai和Bi + n（其中i是正整数，并且n是正整数或负整数并且1≤i≤n且1≤i+n≤M），并且至少生成输出信号Ci，n 一个第二运算电路，用于相对于n的预定值（其中i具有不同的值）产生第一运算电路的输出信号的一部分或全部的总和Sn，或者用于产生由总和Sn确定的预定信号Tn ，以及用于查找Sn或Tn的值的第三运算电路 t分配给多个不同的n值，并且用于确定给定Sn或Tn的最大值或最小值的n值。

    COMPUTING DEVICE
    3.
    发明公开
    COMPUTING DEVICE 失效
    RECHNERVORRICHTUNG。

    公开(公告)号：EP0685808A1

    公开(公告)日：1995-12-06

    申请号：EP94907085.8

    申请日：1994-02-22

    申请人： SHIBATA, Tadashi ,  OHMI, Tadahiro

    发明人： SHIBATA, Tadashi ,  OHMI, Tadahiro ,  KOTANI, Koji, Dept of Electronics Faculty of

    IPC分类号： G06G7/60

    CPC分类号： G06F7/388 ,  G06N3/063 ,  G06N3/0635 ,  G06N99/005

    摘要： A novel computing device capable of performing flexible information processing analogous to that of living things, such as learning, adaption, and self-multiplication, which are essential to implement advanced information processing of the future. The device comprises a plurality of first and second input terminals, and a plurality of operational units which execute a given operation of data signals to be inputted into the first input terminals, and each have at least one terminal for outputting the result of the operation. The output signal from one of the output terminals or the result of a given operational processing of this output signal is inputted into at least one of the second input terminals.

    摘要翻译： 一种能够执行类似于生物的灵活信息处理的新型计算设备，例如学习，适应和自乘，对于实现未来的高级信息处理至关重要。 该装置包括多个第一和第二输入端子，以及执行要输入到第一输入端子的数据信号的给定操作的多个操作单元，并且每个具有用于输出操作结果的至少一个端子。 来自一个输出端子的输出信号或该输出信号的给定操作处理的结果被输入至少一个第二输入端子。

    SEMICONDUCTOR DEVICE
    4.
    发明公开
    SEMICONDUCTOR DEVICE 失效
    HALBLEITERBAUSTEIN。

    公开(公告)号：EP0685806A1

    公开(公告)日：1995-12-06

    申请号：EP94907083.3

    申请日：1994-02-22

    申请人： SHIBATA, Tadashi ,  OHMI, Tadahiro

    发明人： SHIBATA, Tadashi ,  OHMI, Tadahiro ,  YAMASHITA, Takeo, c/o Department of Electronics,

    IPC分类号： G06G7/60

    CPC分类号： G06F7/24 ,  G06N3/0635

    摘要： A device comprising invertor circuit group including two or more invertor circuits formed by neuron MOS transistors; means for applying a first signal voltage common to the two or more invertors of the invertor circuit group to a first input gate of the invertor circuits; means for applying a given second signal to one or more second input gates other than the first input gate of the invertor circuits; a delay circuit for transmitting the variation of the output voltage of at least one of the invertor circuits of the invertor circuit group with a time delay generated by use of the variation with time of the signal voltage of either or both of the first and second signal voltages; a transistor whose ON and OFF is controlled by the signal transmitted from the delay circuit; storage circuits taking in signals by the ON and OFF of the transistor; and means for executing a given logical operation with respect to the output voltage signals generated by the invertor circuit group. The device has a function of storing the result of the logical operation in the storage circuits.

    摘要翻译： 一种包括由神经元MOS晶体管形成的两个或更多个反相器电路的逆变器电路组的器件; 用于将所述逆变器电路组的两个或更多个反相器公共的第一信号电压施加到所述逆变器电路的第一输入栅极的装置; 用于将给定的第二信号施加到除了逆变器电路的第一输入门之外的一个或多个第二输入门的装置; 延迟电路，用于通过使用随着第一和第二信号中的任一个或第二信号的信号电压随时间的变化而产生的时间延迟来发送反相器电路组的至少一个逆变器电路的输出电压的变化 电压; 晶体管的ON和OFF由从延迟电路发送的信号控制; 存储电路通过晶体管的导通和截止来接收信号; 以及用于对由逆变器电路组生成的输出电压信号执行给定逻辑运算的装置。 该装置具有将逻辑运算的结果存储在存储电路中的功能。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    7.
    发明公开
    SEMICONDUCTOR INTEGRATED CIRCUIT 失效
    半导体集成电路。

    公开(公告)号：EP0657934A1

    公开(公告)日：1995-06-14

    申请号：EP93919578.0

    申请日：1993-08-26

    申请人： SHIBATA, Tadashi ,  OHMI, Tadahiro

    发明人： SHIBATA, Tadashi ,  OHMI, Tadahiro

    IPC分类号： H01L27/10 ,  H01L21/82 ,  H01L29/78

    CPC分类号： H03K19/1736 ,  H01L27/11803

    摘要： A semiconductor integrated circuit adaptable to any logic circuits using a common mask with the exception of a mask of metallic wirings so as to drastically improve performance of custom LSIs. The semiconductor integrated circuit comprises a logic circuit having a plurality of input terminals and at least one output terminal. The logic circuit includes a plurality of circuit blocks of the same circuit construction. Each of the circuit blocks has at least two stages of inverter formed by MOS semiconductor devices and at least one layer of a wiring pattern having a different pattern. The output signal of each block is defined by a predetermined function of an input signal.

    SEMICONDUCTOR OPERATIONAL CIRCUIT
    8.
    发明授权
    SEMICONDUCTOR OPERATIONAL CIRCUIT 失效
    半导体电路功能

    公开(公告)号：EP0820030B1

    公开(公告)日：2003-07-02

    申请号：EP96907743.7

    申请日：1996-04-01

    申请人： SHIBATA, Tadashi ,  OHMI, Tadahiro

    发明人： SHIBATA, Tadashi ,  OHMI, Tadahiro

    IPC分类号： G06G7/12 ,  G06G7/26

    CPC分类号： G06G7/26

    摘要： A semiconductor operational circuit capable of instantaneously processing in parallel a large quantity of information. The semiconductor operational circuit executes a predetermined operation of a first signal train of signals A1, A2, ..., AN-1, AN comprising N signals and a second signal train of signals B1, B2, ..., BM-1, BM (where N and M are positive integers) comprising M signals. The circuit includes a plurality of first operational circuits for executing a predetermined operation of Ai and Bi+n (where i is a positive integer and n is an integer and 1

    SEMICONDUCTOR MEMORY
    9.
    发明公开
    SEMICONDUCTOR MEMORY 审中-公开
    半导体存储器

    公开(公告)号：EP1079394A1

    公开(公告)日：2001-02-28

    申请号：EP99913705.2

    申请日：1999-04-19

    申请人： Kabushiki Kaisha Ultraclean Technology Research Institute ,  Ohmi, Tadahiro ,  Shibata, Tadashi

    发明人： OHMI, Tadahiro ,  SHIBATA, Tadashi ,  WEE, Keng Hoong ,  YONEZAWA, Takemi ,  NOZAWA, Toshiyuki ,  NITTA, Takahisa, Kabushiki Kaisha Ultraclean

    IPC分类号： G11C16/02

    CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C27/005 ,  G11C2211/5613

    摘要： The present invention is intended to provide a semiconductor memory circuit that can store analog and many-valued data at high speed and with a high degree of accuracy. The semiconductor memory circuit is characterized by comprising a memory cell in which analog and many-valued signals can be written and stored, a readout circuit having an output terminal which outputs the values stored in the memory cell to the outside as voltages, a comparator having an output terminal which outputs a write end signal when the output terminal voltage of the readout circuit equals to a predetermined voltage, a write voltage controlling circuit having an output terminal which outputs an output voltage corresponding to the analog and many-valued voltage values inputted to an input terminal as a writing voltage of the memory cell, and a write voltage switching circuit having a function which supplies the output voltage of the write voltage controlling circuit to the memory cell and stops to supply the output voltage of the write voltage controlling circuit to the memory cell when the write end signal is outputted to the output terminal of the comparator.

    摘要翻译： 本发明旨在提供一种能够以高速度和高精度存储模拟和多值数据的半导体存储器电路。 半导体存储器电路的特征在于包括：存储单元，其中可以写入和存储模拟和多值信号;读出电路，具有将存储在存储单元中的值作为电压输出到外部的输出端;比较器，具有 输出端子，当读出电路的输出端子电压等于预定电压时输出写入结束信号;写入电压控制电路，具有输出端子，输出端子输出对应于模拟输入电压值和输出的多值电压值的输出电压; 作为所述存储单元的写入电压的输入端子和具有将所述写入电压控制电路的输出电压提供给所述存储单元并停止以将所述写入电压控制电路的输出电压提供给所述存储单元的功能的写入电压切换电路， 当写结束信号被输出到比较器的输出端子时存储单元。

    SEMICONDUCTOR DEVICE
    10.
    发明公开
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：EP0689736A1

    公开(公告)日：1996-01-03

    申请号：EP94904744.0

    申请日：1994-01-20

    申请人： SHIBATA, Tadashi ,  OHMI, Tadahiro

    发明人： SHIBATA, Tadashi ,  OHMI, Tadahiro ,  AU, Rita, Dep. of Electr. Faculty of Engineering

    IPC分类号： H03K19 ,  H03K17 ,  H03M1

    CPC分类号： H03K17/063 ,  H03K17/04163 ,  H03K19/09425 ,  H03M1/361

    摘要： A semiconductor circuit which realizes a source follower having a voltage gain equal to one, a decrease in the time necessary for the source follower to reach its full output voltage. Furthermore, the multiple-valued or analog output voltage can be easily converted to a binary-digital form with this circuit. This semiconductor circuit comprising at least an MOS transistor. A multiple-valued or analog data line is connected to the inputs of multiple-valued comparators, the outputs of said comparators are coupled capacitively to the input gate of a source-follower circuit, and the output of said source-follower circuit is fedback to the data line.