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公开(公告)号：EP0685807A4
公开(公告)日：1997-08-13
申请号：EP94907084
申请日：1994-02-22
申请人： SHIBATA TADASHI , OHMI TADAHIRO
发明人： SHIBATA TADASHI , OHMI TADAHIRO , KOTANI KOJI
CPC分类号： G06N3/0635
摘要： A semiconductor integrated circuit capable of effecting data matching at a high speed is provided by using a simple circuit. The semiconductor integrated circuit includes at least one first input terminal and at least one second input terminal to which a voltage signal is inputted, and at least one output terminal. A predetermined signal is produced at the output terminal when the difference between values expressed by the two signals inputted to the first and second input terminals becomes smaller than a predetermined value. The semiconductor integrated circuit of this invention contains at least two inverters constituted of neuron MOS transistors, and the two signals described above or signals obtained by applying predetermined processing to the two signals are inputted to at least one of the input gates of the inverters.
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公开(公告)号：EP0685808A4
公开(公告)日：1997-05-14
申请号：EP94907085
申请日：1994-02-22
申请人： SHIBATA TADASHI , OHMI TADAHIRO
发明人： SHIBATA TADASHI , OHMI TADAHIRO , KOTANI KOJI
CPC分类号： G06F7/388 , G06N3/063 , G06N3/0635 , G06N99/005
摘要： A novel computing device capable of performing flexible information processing analogous to that of living things, such as learning, adaption, and self-multiplication, which are essential to implement advanced information processing of the future. The device comprises a plurality of first and second input terminals, and a plurality of operational units which execute a given operation of data signals to be inputted into the first input terminals, and each have at least one terminal for outputting the result of the operation. The output signal from one of the output terminals or the result of a given operational processing of this output signal is inputted into at least one of the second input terminals.
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3.发明公开SEMICONDUCTOR CIRCUIT FOR ARITHMETIC OPERATION AND METHOD OF ARITHMETIC OPERATION 审中-公开HALBLEITERKREISLAUFFÜRARITHMETISCHE HANDLUNGEN UND VERFAHRENFÜRARTHMETISCHE HANDLUNGEN
公开(公告)号：EP1039372A4
公开(公告)日：2005-02-02
申请号：EP98961396
申请日：1998-12-17
发明人： OHMI TADAHIRO , IMAI MAKOTO , NOZAWA TOSHIYUKI , FUJIBAYASHI MASANORI , KOTANI KOJI , SHIBATA TADASHI , NITTA TAKAHISA
CPC分类号： G06F7/4824 , G06F7/506
摘要： A semiconductor circuit for arithmetic operation, which uses a reduced circuit area and provides high-speed processing by restricting nonessentials. The semiconductor circuit comprises an arithmetic circuit (adders 1-3) and delay means (memory 4). The arithmetic circuit includes arithmetic units for operation on input data, and they operate on digits of input data in a period of operation time, and produce results of operation, together with data corresponding to a carry, if any. The output from the arithmetic circuit is delayed by one period of operation time through the delay means.
摘要翻译： 提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来提高处理数据的速率并减小电路的面积。 提供了一种用于计算输入数据的计算单元，该计算单元在计算时间单位内计算输入数字数据，并输出表示通过计算获得的结果的计算结果，并且如果在计算中产生进位，则计算电路（ 用于输出表示该进位的进位数据的加法器1-3）和用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。
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公开(公告)号：EP1487112A4
公开(公告)日：2005-12-21
申请号：EP03705222
申请日：2003-02-17
申请人： OHMI TADAHIRO
发明人： OHMI TADAHIRO , MOCHIZUKI KENJI , KOTANI KOJI
CPC分类号： G06K9/6202 , H03M7/30 , H03M7/3082 , H03M7/3084 , H04N19/94
摘要： Data compression using vector quantization is performed at a high speed by using hardware. Among a plurality of template patterns, a template pattern most similar to the input pattern is searched. For this, a template pattern calculating similarity by using feature amounts of the input pattern and the template pattern is selected. When calculating the similarity between the selected template pattern and the input pattern, the calculation is performed by a bit serial way so as to reduce the number of templates requiring matching by a pattern matching processing in the vector quantization and reduce the number of cycles required for calculation of the matching, thereby executing the data compression using the vector quantization at a high speed.
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公开(公告)号：EP1455393A4
公开(公告)日：2006-01-25
申请号：EP02786074
申请日：2002-12-10
申请人： OHMI TADAHIRO , TOKYO ELECTRON LTD
发明人： OHMI TADAHIRO , KOTANI KOJI , SUGAWA SH
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/04 , H01L29/786
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823821 , H01L27/092 , H01L27/0922 , H01L29/66795 , H01L29/7851
摘要： A CMOS device comprises a structure formed on the (100) face of a silicon substrate and having another crystal face, and a p-channel MOS transistor and an n-channel MOS transistor each having a high-quality gate insulating film formed on the structure by microwave plasma processing and a gate electrode formed on the gate insulating film. The dimensions and shape of the structure are so set that the carrier mobility in the p-channel MOS transistor and that in the N-channel MOS transistor are balanced.
摘要翻译： CMOS器件包括在硅衬底的（100）面上形成并具有另一晶面的结构，以及在结构上形成有高质量栅绝缘膜的p沟道MOS晶体管和n沟道MOS晶体管 通过微波等离子体处理和在栅绝缘膜上形成的栅电极。 该结构的尺寸和形状被设定为使得p沟道MOS晶体管和N沟道MOS晶体管中的载流子迁移率平衡。
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公开(公告)号：EP1681715A4
公开(公告)日：2009-12-30
申请号：EP04818177
申请日：2004-11-02
申请人： OHMI TADAHIRO , TOKYO ELECTRON LTD
发明人： OHMI TADAHIRO , NOZAWA TOSHIHISA , MORITA OSAMU , YUASA TAMAKI , KOTANI KOJI
IPC分类号： H01J37/32 , C23C16/455 , H01L21/3065 , H01L21/31
CPC分类号： H01J37/32192 , C23C16/4411 , C23C16/45572 , C23C16/511 , H01J37/3244 , H01J37/32724
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