公开(公告)号：EP4345874A2

公开(公告)日：2024-04-03

申请号：EP23187220.1

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： HWANG, Donghoon ,  KANG, Myungil ,  GWAK, Minchan ,  KIM, Kyungho ,  CHO, Kyung Hee ,  CHOI, Doyoung

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A three-dimensional semiconductor device includes a first active region on a substrate (100), the first active region including a lower channel pattern and a lower source/drain pattern (LSD1) connected to the lower channel pattern, a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern (USD1) connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a lower contact (LCT) electrically connected to the lower source/drain pattern, the lower contact having a bar shape extending on the lower source/drain pattern in a first direction, a first active contact (AC1) coupled to the lower contact, and a second active contact (AC2) coupled to the upper source/drain pattern. A first width of the lower source/drain pattern in a second direction is larger than a second width of the lower contact in the second direction.

公开(公告)号：EP4456692A1

公开(公告)日：2024-10-30

申请号：EP23219687.3

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： KIM, Jeewoong ,  CHO, Kyung Hee

IPC: H10B10/00 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092

Abstract: A semiconductor memory device includes a substrate including a first surface and a second surface, which are opposite to each other, a lower active region on the first surface, the lower active region including a lower gate electrode and a lower active contact, which are spaced apart from each other, an upper active region stacked on the lower active region, the upper active region including an upper gate electrode and an upper active contact, which are spaced apart from each other, a first metal layer on the first surface, and a back-side metal layer on the second surface. The back-side metal layer includes a first shared pad electrically connecting the lower gate electrode to the lower active contact. The first metal layer includes a second shared pad electrically connecting the upper gate electrode to the upper active contact.

公开(公告)号：EP4451331A1

公开(公告)日：2024-10-23

申请号：EP24151217.7

申请日：2024-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： HWANG, Inchan ,  CHO, Kyung Hee ,  LEE, Seunghun

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H10B10/00 ,  H01L23/528

Abstract: A semiconductor memory device comprising a substrate having first and second surfaces opposite to each other, a lower active region on the first surface and including a first lower gate electrode and a first lower active contact, an upper active region on the lower active region and including a first upper gate electrode and a first upper active contact that vertically overlap at least a part of the first lower active contact, a first connection structure vertically connecting the first upper active contact to the first lower active contact, a first metal layer on the first surface, and a backside metal layer on the second surface. The first upper gate electrode and the first lower gate electrode are connected and form a first gate electrode. The first metal layer includes a first node line electrically connecting the first gate electrode to the first upper active contact.

公开(公告)号：EP4345874A3

公开(公告)日：2024-05-22

申请号：EP23187220.1

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： HWANG, Donghoon ,  KANG, Myungil ,  GWAK, Minchan ,  KIM, Kyungho ,  CHO, Kyung Hee ,  CHOI, Doyoung

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L27/0688 ,  H01L21/823871 ,  H01L21/823842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/8221 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/78696

Abstract: A three-dimensional semiconductor device includes a first active region on a substrate (100), the first active region including a lower channel pattern and a lower source/drain pattern (LSD1) connected to the lower channel pattern, a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern (USD1) connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a lower contact (LCT) electrically connected to the lower source/drain pattern, the lower contact having a bar shape extending on the lower source/drain pattern in a first direction, a first active contact (AC1) coupled to the lower contact, and a second active contact (AC2) coupled to the upper source/drain pattern. A first width of the lower source/drain pattern in a second direction is larger than a second width of the lower contact in the second direction.