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公开(公告)号：EP2187453A3
公开(公告)日：2011-05-25
申请号：EP09175236.0
申请日：2009-11-06
发明人： Chae, Su-hee , Jeong, Hyung-su , Yang, Moon-seung , Kim, Taek , Kim, Jun-youn , Park, Jae-chul , Kim, Kyoung-kook , Park, Young-soo
CPC分类号： H01L33/0079 , H01L33/12
摘要： Provided is a light emitting diode (LED) manufactured by using a wafer bonding method and a method of manufacturing a LED by using a wafer bonding method. The wafer bonding method may include interposing a stress relaxation layer (33) formed of a metal between a semiconductor layer (20) and a bonding substrate (31). When the stress relaxation layer is used, stress between the bonding substrate and a growth substrate may be offset due to the flexibility of metal, and accordingly, bending or warpage of the bonding substrate may be reduced or prevented.
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公开(公告)号：EP2704184B1
公开(公告)日：2019-06-19
申请号：EP13182592.9
申请日：2013-09-02
发明人： Kim, Jun-youn , Kim, Joo-sung , Yang, Moon-seung
IPC分类号： H01L21/20
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3.发明公开Silicon substrate, epitaxial structure including the same, and method of manufacturing the silicon substrate 审中-公开硅藻土，上海大学学报（社会科学版）und ats ats ats ats ats ats ats ats ats ats ats ats ats
公开(公告)号：EP2602810A1
公开(公告)日：2013-06-12
申请号：EP12184304.9
申请日：2012-09-13
发明人： Kim, Jun-youn , Kim, Jae-kyun , Chae, Su-hee , Hong, Hyun-gi
IPC分类号： H01L21/02
CPC分类号： C30B25/186 , C30B29/06 , C30B29/403 , H01L21/02381 , H01L21/0243 , H01L21/0254 , H01L21/02639 , H01L21/02658
摘要： Crack formation and propagation in a silicon substrate may be reduced by forming a crack reducing portion. The silicon substrate includes a silicon main portion and a silicon edge portion formed around the silicon main portion. The crack reducing portion is formed on the silicon edge portion of the silicon substrate such that directions of crystal faces in the crack reducing portion are randomly oriented.
摘要翻译： 通过形成裂纹减少部分可以减少硅衬底中的裂纹形成和传播。 硅基板包括硅主体部分和形成在硅主体部分周围的硅边缘部分。 在硅基板的硅边缘部分上形成裂纹减少部分，使得裂纹缩小部分中的晶面的方向随机取向。
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公开(公告)号：EP2434532A1
公开(公告)日：2012-03-28
申请号：EP11183069.1
申请日：2011-09-28
发明人： Tak, Young-jo , Lee, Jae-won , Park, Young-soo , Kim, Jun-youn
IPC分类号： H01L21/02
CPC分类号： H01L21/0254 , H01L21/02378 , H01L21/02381 , H01L21/02458 , H01L21/02502 , H01L21/02505 , H01L21/02507 , H01L21/0259 , H01L21/02642 , H01L21/02664 , H01L33/007 , H01L33/12 , H01L33/32
摘要： A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.
摘要翻译： 一种半导体器件包括衬底，衬底上的缓冲层以及缓冲层上的多个氮化物半导体层。 该半导体器件还包括至少一个掩模层和在该多个氮化物半导体层之间的至少一个中间层。 该至少一个中间层位于至少一个掩模层上。
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5.发明公开
公开(公告)号：EP2575181A3
公开(公告)日：2014-05-21
申请号：EP12185963.1
申请日：2012-09-25
发明人： Kim, Jun-youn , Lee, Jae-won , Choi, Hyo-ji
IPC分类号： H01L29/778 , H01L21/338 , H01L29/06 , H01L29/10 , H01L29/20 , H01L29/423
CPC分类号： H01L29/66431 , H01L29/0649 , H01L29/1066 , H01L29/1075 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/7786
摘要： A high electron mobility transistor (HEMT) includes a substrate (30), an HEMT stack (60) spaced apart from the substrate, and a pseudo-insulation layer (PIL) (20) disposed between the substrate and the HEMT stack. The PIL includes at least two materials having different phases. The PIL defines an empty space (50) that is wider at an intermediate portion than at an entrance of the empty space.
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6.发明公开Semiconductor buffer structure, semiconductor device including the same, and method of manufacturing semiconductor device using semiconductor buffer structure 审中-公开半导体缓冲结构，使半导体器件和工艺用于使用所述半导体缓冲结构的半导体器件制造
公开(公告)号：EP2696365A3
公开(公告)日：2014-02-26
申请号：EP13179953.8
申请日：2013-08-09
发明人： Tak, Young-jo , Kim, Jae-kyun , Kim, Joo-sung , Kim, Jun-youn , Lee, Jae-won , Choi, Hyo-ji
CPC分类号： H01L33/12 , H01L21/02381 , H01L21/02458 , H01L21/02505 , H01L21/02507 , H01L21/0251 , H01L21/0254 , H01L33/0066 , H01L33/0079
摘要： Provided is a method of manufacturing a semiconductor device. The method includes preparing a silicon substrate, forming a buffer layer on the silicon substrate, and forming a nitride semiconductor layer on the buffer layer. The buffer layer includes a first layer, a second layer, and a third layer. The first layer includes Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) and has a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer is formed on the first layer, includes Al x In y Ga 1-x-y N (0≤x x In y Ga 1-x-y N (0≤x
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7.发明公开High electron mobility transistor and method of manufacturing the same 审中-公开晶体管切割机Elektronenmobilitätund Herstellungsverfahrendafür
公开(公告)号：EP2575181A2
公开(公告)日：2013-04-03
申请号：EP12185963.1
申请日：2012-09-25
发明人： Kim, Jun-youn , Lee, Jae-won , Choi, Hyo-ji
IPC分类号： H01L29/778 , H01L29/06 , H01L29/20 , H01L29/423
CPC分类号： H01L29/66431 , H01L29/0649 , H01L29/1066 , H01L29/1075 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/7786
摘要： A high electron mobility transistor (HEMT) includes a substrate (30), an HEMT stack (60) spaced apart from the substrate, and a pseudo-insulation layer (PIL) (20) disposed between the substrate and the HEMT stack. The PIL includes at least two materials having different phases. The PIL defines an empty space (50) that is wider at an intermediate portion than at an entrance of the empty space.
摘要翻译： 高电子迁移率晶体管（HEMT）包括衬底（30），与衬底间隔开的HEMT堆叠（60）以及设置在衬底和HEMT堆叠之间的伪绝缘层（PIL）（20）。 PIL包括至少两种具有不同相位的材料。 PIL定义在中间部分比在空白空间的入口处更宽的空白空间（50）。
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8.发明公开Substrate Structures and Methods of Manufacturing the same 审中-公开Substratstrukturen und Herstellungsverfahrendafür
公开(公告)号：EP2287924A2
公开(公告)日：2011-02-23
申请号：EP10172937.4
申请日：2010-08-16
发明人： Kim, Jun-youn , Jeong, Hyung-su , Lee, Jae-won , Tak, Young-jo , Hong, Hyun-gi
CPC分类号： H01L33/007 , H01L21/0237 , H01L21/02439 , H01L21/0254 , H01L21/02639 , H01L21/0265 , H01L27/156 , H01L33/0079 , H01L33/12 , H01L33/20
摘要： A substrate structure is manufactured by forming a protrusion area (21) of a substrate under a buffer layer (22), and forming a semiconductor layer (23) on the buffer layer, thereby separating the substrate from the buffer layer except in an area where the protrusion is formed. The semiconductor layer on the buffer layer not contacting the substrate has freestanding characteristics, and dislocation or cracks may be reduced and/or prevented.
摘要翻译： 通过在缓冲层（22）的下方形成基板的突出区域（21），在缓冲层上形成半导体层（23），将基板从缓冲层分离，制造基板结构体， 形成突起。 不与衬底接触的缓冲层上的半导体层具有独立的特性，并且可以减少和/或阻止位错或裂纹。
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公开(公告)号：EP2843714B1
公开(公告)日：2020-10-07
申请号：EP14182021.7
申请日：2014-08-22
发明人： Kim, Jae-kyun , Kim, Joo-sung , Kim, Jun-youn , Park, Young-soo , Tak, Young-jo
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10.发明公开Semiconductor buffer structure, semiconductor device including the semiconductor buffer structure, and method of manufacturing the semiconductor device using the semiconductor buffer structure 审中-公开半导体缓冲结构中，具有半导体装置的制造具有半导体缓冲结构的半导体缓冲器的结构和方法的半导体装置
公开(公告)号：EP2869333A1
公开(公告)日：2015-05-06
申请号：EP14189626.6
申请日：2014-10-21
发明人： Kim, Jun-youn , Tak, Young-jo , Kim, Jae-kyun , Kim, Joo-sung , Park, Young-soo , Chae, Su-hee
IPC分类号： H01L21/20
CPC分类号： H01L33/0025 , H01L21/02381 , H01L21/02433 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L33/007 , H01L33/0079 , H01L33/12 , H01L33/32
摘要： A semiconductor buffer structure includes a silicon substrate, a nucleation layer formed on the silicon substrate, and a buffer layer formed on the nucleation layer. The buffer layer includes a first layer formed of a nitride semiconductor material having a uniform composition rate, a second layer formed of the same material as the nucleation layer on the first layer, and a third layer formed of the same material with the same composition ratio as the first layer on the second layer.
摘要翻译： 一种半导体缓冲结构包括一硅衬底，在硅衬底的成核层形成，并且形成在成核层上的缓冲层。 所述缓冲层包括形成具有均匀组成率，形成在相同的材料第一层上的成核层的第二层，并用相同的组成比相同的材料形成的第三层的氮化物半导体材料的第一层 作为第二层上的第一层。
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