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1.发明授权PRE-CHARGE DURING PROGRAMMIMG FOR 3D MEMORY USING GATE- INDUCED DRAIN LEAKAGE 有权预充电与栅极感应流量泄漏的三维存储器编程期间
公开(公告)号：EP2912666B1
公开(公告)日：2016-09-28
申请号：EP13783805.8
申请日：2013-10-21
发明人： DUNGA, Mohan , DONG, Yingda , OU, Wendy
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C2213/71
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2.发明授权
公开(公告)号：EP2856469B1
公开(公告)日：2016-09-14
申请号：EP13722235.2
申请日：2013-05-02
CPC分类号： G11C16/14 , G11C7/1006 , G11C11/5635 , G11C16/0483 , G11C16/16
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公开(公告)号：EP3262686A1
公开(公告)日：2018-01-03
申请号：EP16730940.0
申请日：2016-05-31
发明人： HSIUNG, Chia-Lin , TOYAMA, Fumiaki , DUNGA, Mohan
IPC分类号： H01L27/115 , G11C11/56 , G11C16/04 , G11C16/24 , G11C16/26
CPC分类号： G11C16/26 , G11C7/1006 , G11C7/106 , G11C7/1087 , G11C11/5642 , G11C16/0483 , G11C2207/002 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11556
摘要： A non-volatile storage system is provided. The non-volatile storage system includes a memory array that includes a plurality of bit lines and a plurality of sense blocks, a plurality of bit line select transistors arranged in a bit line select transistor array, each bit line select transistor coupled between a corresponding one of the bit lines and a corresponding one of the sense blocks, the bit line select transistor array including an edge bit line select transistor adjacent an edge of the bit line select transistor array, and a first dummy bit line select transistor adjacent the edge bit line select transistor.
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