公开(公告)号：EP2736067A1

公开(公告)日：2014-05-28

申请号：EP12814532.3

申请日：2012-05-25

申请人： Sumitomo Electric Industries, Ltd. ,  National University Corporation Nara Institute of Science and Technology

发明人： MASUDA, Takeyoshi ,  HATAYAMA, Tomoaki

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/12 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/046 ,  H01L21/324 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068

摘要： A method for manufacturing a MOSFET (1) includes the steps of: introducing an impurity into a silicon carbide layer (10); forming a carbon layer (81) in a surface layer portion of the silicon carbide layer (10) having the impurity introduced therein, by selectively removing silicon from the surface layer portion; and activating the impurity by heating the silicon carbide layer (10) having the carbon layer (81) formed therein.

摘要翻译： 一种用于制造MOSFET（1）的方法包括以下步骤：将杂质引入碳化硅层（10）中; 通过从所述表层部分选择性地去除硅，在其中引入了所述杂质的所述碳化硅层（10）的表层部分中形成碳层（81） 并通过加热其中形成有碳层（81）的碳化硅层（10）来激活杂质。

公开(公告)号：EP2784821A1

公开(公告)日：2014-10-01

申请号：EP12851689.5

申请日：2012-09-12

申请人： Sumitomo Electric Industries, Ltd. ,  National University Corporation Nara Institute of Science and Technology

发明人： MASUDA, Takeyoshi ,  HATAYAMA, Tomoaki

IPC分类号： H01L29/12 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068

摘要： A silicon carbide layer (50) includes a first region (51) having a first conductivity type, a second region (52) provided on the first region (51) and having a second conductivity type, and a third region (53) provided on the second region (52) and having the first conductivity type. A trench (TR) having an inner surface is formed in the silicon carbide layer (50). The trench (TR) penetrates the second and third regions (52, 53). The inner surface of the trench (TR) has a first side wall (SW1) and a second side wall (SW2) located deeper than the first side wall (SW1) and having a portion made of the second region (52). Inclination of the first side wall (SW1) is smaller than inclination of the second side wall (SW2).

摘要翻译： 碳化硅层（50）包括具有第一导电类型的第一区域（51），设置在第一区域（51）上并具有第二导电类型的第二区域（52）以及设置在第一区域 第二区域（52）并且具有第一导电类型。 在碳化硅层（50）中形成具有内表面的沟槽（TR）。 沟槽（TR）穿透第二和第三区域（52,53）。 沟槽（TR）的内表面具有位于比第一侧壁（SW1）更深并且具有由第二区域（52）制成的部分的第一侧壁（SW1）和第二侧壁（SW2）。 第一侧壁（SW1）的倾斜小于第二侧壁（SW2）的倾斜。

公开(公告)号：EP2804215B1

公开(公告)日：2018-02-21

申请号：EP12864703.9

申请日：2012-11-27

申请人： Sumitomo Electric Industries, Ltd. ,  National University Corporation Nara Institute of Science and Technology

发明人： HIYOSHI, Toru ,  MASUDA, Takeyoshi ,  HATAYAMA, Tomoaki

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/12 ,  H01L29/739

CPC分类号： H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/3247 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7397

摘要： A silicon carbide layer is thermally etched by supplying the silicon carbide layer with a process gas that can chemically react with silicon carbide, while heating the silicon carbide layer. With this thermal etching, a carbon film (50) is formed on the silicon carbide layer. Heat treatment is provided to the silicon carbide layer to diffuse carbon from the carbon film (50) into the silicon carbide layer.

公开(公告)号：EP2804215A1

公开(公告)日：2014-11-19

申请号：EP12864703.9

申请日：2012-11-27

申请人： Sumitomo Electric Industries, Ltd. ,  National University Corporation Nara Institute of Science and Technology

发明人： HIYOSHI, Toru ,  MASUDA, Takeyoshi ,  HATAYAMA, Tomoaki

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/12 ,  H01L29/739

CPC分类号： H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/3247 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7397

摘要： A silicon carbide layer is thermally etched by supplying the silicon carbide layer with a process gas that can chemically react with silicon carbide, while heating the silicon carbide layer. With this thermal etching, a carbon film (50) is formed on the silicon carbide layer. Heat treatment is provided to the silicon carbide layer to diffuse carbon from the carbon film (50) into the silicon carbide layer.

摘要翻译： 碳化硅层通过向碳化硅层供应可与碳化硅发生化学反应的处理气体同时加热碳化硅层来热蚀刻。 通过该热蚀刻，在碳化硅层上形成碳膜（50）。 对碳化硅层提供热处理以将碳从碳膜（50）扩散到碳化硅层中。

公开(公告)号：EP2348530A1

公开(公告)日：2011-07-27

申请号：EP09817584.7

申请日：2009-08-07

申请人： Sumitomo Electric Industries, Ltd. ,  National University Corporation Nara Institute of Science and Technology

发明人： HARADA, Shin ,  TAMASO, Hideto ,  HATAYAMA, Tomoaki

IPC分类号： H01L29/12 ,  H01L21/28 ,  H01L21/336 ,  H01L21/337 ,  H01L29/417 ,  H01L29/78 ,  H01L29/808

CPC分类号： H01L29/7802 ,  H01L21/046 ,  H01L21/0485 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/66068 ,  H01L29/808 ,  H01L29/8613

摘要： Provided is a silicon carbide semiconductor device capable of lowering the contact resistance of an ohmic electrode and achieving high reverse breakdown voltage characteristics. A semiconductor device (1) includes a substrate (2) and a p + region (25) as an impurity layer. The substrate (2) of the first conductive type (n type) is made of silicon carbide and has a dislocation density of 5 × 10 3 cm -2 or less. The p + region (25) is formed on the substrate (2), in which the concentration of the conductive impurities having the second conductive type different from the first conductive type is 1 × 10 20 cm -3 or more and 5 × 10 21 cm -3 or less.

摘要翻译： 提供了能够降低欧姆电极的接触电阻并实现高反向击穿电压特性的碳化硅半导体器件。 半导体器件（1）包括作为杂质层的衬底（2）和p +区（25）。 第一导电型（n型）的基板（2）由碳化硅构成，位错密度为5×10 3 cm -2以下。 p +区域（25）形成在基板（2）上，其中具有不同于第一导电类型的第二导电类型的导电杂质的浓度为1×10 20 cm -3以上且5×10 21 cm -3以下。

公开(公告)号：EP2348530B1

公开(公告)日：2016-03-09

申请号：EP09817584.7

申请日：2009-08-07

申请人： Sumitomo Electric Industries, Ltd. ,  National University Corporation Nara Institute of Science and Technology

发明人： HARADA, Shin ,  TAMASO, Hideto ,  HATAYAMA, Tomoaki

IPC分类号： H01L29/12 ,  H01L21/28 ,  H01L21/336 ,  H01L21/337 ,  H01L29/417 ,  H01L29/78 ,  H01L29/808 ,  H01L29/861

CPC分类号： H01L29/7802 ,  H01L21/046 ,  H01L21/0485 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/66068 ,  H01L29/808 ,  H01L29/8613

摘要： Provided is a silicon carbide semiconductor device capable of lowering the contact resistance of an ohmic electrode and achieving high reverse breakdown voltage characteristics. A semiconductor device (1) includes a substrate (2) and a p + region (25) as an impurity layer. The substrate (2) of the first conductive type (n type) is made of silicon carbide and has a dislocation density of 5 × 10 3 cm -2 or less. The p + region (25) is formed on the substrate (2), in which the concentration of the conductive impurities having the second conductive type different from the first conductive type is 1 × 10 20 cm -3 or more and 5 × 10 21 cm -3 or less.

公开(公告)号：EP2784805A1

公开(公告)日：2014-10-01

申请号：EP12851007.0

申请日：2012-10-02

申请人： Sumitomo Electric Industries, Ltd. ,  National University Corporation Nara Institute of Science and Technology

发明人： MASUDA, Takeyoshi ,  HATAYAMA, Tomoaki

IPC分类号： H01L21/336 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/329 ,  H01L29/06 ,  H01L29/12 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/868

CPC分类号： H01L29/8613 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/0475 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/045 ,  H01L29/06 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/739 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/868 ,  Y10S438/931

摘要： On a substrate (1), a silicon carbide layer (19) provided with a main surface is formed. A mask (17) is formed to cover a portion of the main surface of the silicon carbide layer (19). The main surface of the silicon carbide layer (19) on which the mask (17) is formed is thermally etched using chlorine-based gas so as to provide the silicon carbide layer (19) with a side surface (SS) inclined relative to the main surface. The step of thermally etching is performed in an atmosphere in which the chlorine-based gas has a partial pressure of 50% or smaller.

摘要翻译： 在衬底（1）上，形成具有主表面的碳化硅层（19）。 掩模（17）形成为覆盖碳化硅层（19）的主表面的一部分。 使用氯基气体对其上形成有掩模（17）的碳化硅层（19）的主表面进行热蚀刻，以便为碳化硅层（19）提供相对于所述碳化硅层（19）倾斜的侧表面 主表面。 热蚀刻工序在氯系气体的分压为50％以下的气氛下进行。

公开(公告)号：EP2750198A1

公开(公告)日：2014-07-02

申请号：EP12827910.6

申请日：2012-08-27

申请人： National University Corporation Nara Institute of Science and Technology

发明人： HATAYAMA, Tomoaki ,  KOKETSU, Hidenori ,  TODOKORO, Yoshihiro

IPC分类号： H01L29/78 ,  H01L21/205 ,  H01L21/336 ,  H01L29/12

CPC分类号： H01L21/30604 ,  H01L21/0475 ,  H01L21/30617 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7813

摘要： Provided are a technology that simply forms a particular crystal surface such as a {03-38} surface having high carrier mobility in trench sidewalls and a SiC semiconductor element where most of the trench sidewalls appropriate for a channel member are formed from {03-38} surfaces. A trench structure formed in a (0001) surface or an off-oriented surface of a (0001) surface with an offset angle 8° or lower of SiC is provided. The channel member is in the trench structure. At least 90% of the area of the channel member is a {03-38} surface or a surface that a {03-38} surface offset by an angle from -8° to 8 ° in the direction. Specifically, the trench sidewalls are finished to {03-38} surfaces by applying a thermal etching to a trench with (0001) surfaces of SiC. Thermal etching is conducted in a chlorine atmosphere above 800 °C with nitrogen gas as the carrier.

摘要翻译： 提供了一种简单地形成特定晶体表面的技术，例如在沟槽侧壁中具有高载流子迁移率的{03-38}表面，以及适合于沟道部件的大多数沟槽侧壁的SiC半导体元件由{03-38 }表面。 提供了形成在（0001）表面或（0001）表面的偏移角为8°或更小的SiC的表面的（0001）表面的沟槽结构。 通道构件处于沟槽结构。 通道构件的面积的至少90％是{03-38}表面或{01-38}表面在<1-100>方向偏移-8°至8°的角度的表面。 具体地说，通过对具有SiC的（0001）表面的沟槽进行热蚀刻，将沟槽侧壁完成到{03-38}表面。 用氮气作为载体，在800℃以上的氯气气氛中进行热蚀刻。