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    METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES
    3.
    发明公开
    METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES 审中-公开
    工艺生产高POET器件随着集成电路

    公开(公告)号：EP2705525A2

    公开(公告)日：2014-03-12

    申请号：EP12779549.0

    申请日：2012-05-01

    申请人： Synopsys, Inc.

    发明人： MOROZ, Victor ,  LIN, Xi-wei

    IPC分类号： H01L21/027

    CPC分类号： G06F17/5068 ,  H01L21/3086

    摘要： An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.

    RECLAIMING USABLE INTEGRATED CIRCUIT CHIP AREA NEAR THROUGH-SILICON VIAS
    6.
    发明公开
    RECLAIMING USABLE INTEGRATED CIRCUIT CHIP AREA NEAR THROUGH-SILICON VIAS 有权
    再生的将合适的IC芯片面积近SILICON WELLS

    公开(公告)号：EP2524392A1

    公开(公告)日：2012-11-21

    申请号：EP11700309.5

    申请日：2011-01-10

    申请人： Synopsys, Inc.

    发明人： MOROZ, Victor

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    摘要： Roughly described, an integrated circuit device includes a substrate including a via passing therethrough, a strained electrically conductive first material in the via, the first material tending to introduce first stresses into the substrate, and a strained second material in the via, the second material tending to introduce second stresses into the substrate which at least partially cancel the first stresses. In an embodiment, SiGe is grown epitaxially on the inside sidewall of the via in the silicon wafer. SiO2 is then formed on the inside surface of the SiGe, and metal is formed down the center. The stresses introduce by the SiGe tend to counteract the stresses introduced by the metal, thereby reducing or eliminating undesirable stress in the silicon and permitting the placement of transistors in close proximity to the TSV.