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14 条记录 (耗时 0.011 秒)

    Phase detector
    2.
    发明授权
    Phase detector 有权

    公开(公告)号：EP1816741B1

    公开(公告)日：2018-10-03

    申请号：EP07108304.2

    申请日：2001-07-02

    申请人： Texas Instruments Incorporated

    发明人： Staszewski, Robert B. ,  Leipold, Dirk

    IPC分类号： H03D13/00 ,  H03L7/091 ,  H03L7/085

    CPC分类号： H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L2207/50

    摘要： A digital fractional phase detector (200) is provided to realize a frequency synthesizer architecture (100) that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO (104) and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector (200) is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock (110) and a reference clock by using a time-to-digital converter (201) to express the time difference as a digital word for use by the frequency synthesizer.

    Phase detector
    4.
    发明公开
    Phase detector 审中-公开
    相位检测器

    公开(公告)号：EP1816741A1

    公开(公告)日：2007-08-08

    申请号：EP07108304.2

    申请日：2001-07-02

    申请人： Texas Instruments Incorporated

    发明人： Staszewski, Robert B. ,  Leipold, Dirk

    IPC分类号： H03D13/00 ,  H03L7/091 ,  H03L7/085

    CPC分类号： H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L2207/50

    摘要： There is provided a digital fractional phase detector (200) comprising a first input to receive an oscillator clock signal (CKV) and a second input to receive a frequency reference clock signal (FREF). A time-to-digital converter TDC (201) is coupled to said first input and said second input, said TDC producing a signal indicative of timing difference between said oscillator clock signal and said frequency clock signal. A normalizer (NORM) is coupled to said TDC (201), said normalizer producing an output, wherein said output is normalized to a period of said oscillator clock signal. Also provided is a method of generating a fractional phase error signal whereby a timing difference between an oscillator clock signal and a frequency reference clock signal is obtained, and then normalizing said timing difference to a period of said oscillator clock signal.

    摘要翻译： 提供了一种数字分数相位检测器（200），包括接收振荡器时钟信号（CKV）的第一输入端和接收频率参考时钟信号（FREF）的第二输入端。 时间数字转换器TDC（201）耦合到所述第一输入端和所述第二输入端，所述TDC产生表示所述振荡器时钟信号与所述频率时钟信号之间的定时差的信号。 归一化器（NORM）耦合到所述TDC（201），所述归一化器产生输出，其中所述输出归一化为所述振荡器时钟信号的周期。 还提供一种产生分数相位误差信号的方法，由此获得振荡器时钟信号和频率基准时钟信号之间的定时差，然后将所述定时差归一化为所述振荡器时钟信号的周期。

    Receiver using DC Offset Adjustment for optimal IP2
    6.
    发明公开
    Receiver using DC Offset Adjustment for optimal IP2 有权
    IP2优化技术

    公开(公告)号：EP1786097A1

    公开(公告)日：2007-05-16

    申请号：EP06123669.1

    申请日：2006-11-08

    申请人： Texas Instruments Incorporated

    发明人： Muhammed, Khurram ,  Leipold, Dirk

    IPC分类号： H03D3/00

    CPC分类号： H03D3/008

    摘要： The invention (100) provides an offset balancer (130) for use with a differential mixer employing a wireless reception and an offset quantifier (131) configured to indicate an existing DC offset of the mixer corresponding to an existing second-order intercept point applicable to the wireless reception. In one embodiment, the offset balancer includes an offset adjuster (132) coupled to the offset quantifier and configured to provide an offset adjustment to the existing DC offset based on increasing the existing second-order intercept point.

    摘要翻译： 本发明（100）提供了一种与使用无线接收的差分混合器一起使用的偏移平衡器（130）和被配置为指示对应于现有二阶截点的现有DC偏移量的偏移量化器（131） 无线接收。 在一个实施例中，偏移平衡器包括偏移调整器（132），偏移调整器（132）耦合到偏移量化器并且被配置为基于增加现有的二阶截取点来提供对现有DC偏移的偏移调整。

    Transmit filter using a reference clock that is no integer multiple of the symbol clock
    7.
    发明公开
    Transmit filter using a reference clock that is no integer multiple of the symbol clock 有权
    西班牙文德文参考文献

    公开(公告)号：EP1286510A1

    公开(公告)日：2003-02-26

    申请号：EP02102201.7

    申请日：2002-08-20

    申请人： Texas Instruments Incorporated

    发明人： Staszewski, Robert B ,  Leipold, Dirk

    IPC分类号： H04L25/03

    CPC分类号： H03H17/0283 ,  H04L7/0029

    摘要： A transmit filter (100) receives a stream of data symbols (DT_TX) at a baseband symbol clock rate. An available clock is used to generate sample points for producing a generating an oversampled signal. The available clock is independent from the baseband symbol clock, and does not need to be an integer multiple of the clock. Upon identifying a start sequence in the data stream, a phase tracking circuit (106) is used to determine a current position relative to the baseband symbol clock. A state circuit (104) stores the last three, or more, data symbols. Based on the last three data symbols (which determines the shape of the curve for the current data symbol) and the current position (which determines the current position on the curve), a filter circuit (108) generates a sample point.

    摘要翻译： 发射滤波器（100）以基带符号时钟速率接收数据符号流（DT_TX）。 使用可用的时钟来产生用于产生过采样信号的采样点。 可用时钟独立于基带符号时钟，不需要是时钟的整数倍。 在识别数据流中的起始序列时，使用相位跟踪电路（106）来确定相对于基带符号时钟的当前位置。 状态电路（104）存储最后三个或更多数据符号。 基于最后三个数据符号（其确定当前数据符号的曲线的形状）和当前位置（其确定曲线上的当前位置），滤波器电路（108）产生采样点。

    Sub-sampling mixer
    8.
    发明公开
    Sub-sampling mixer 有权
    Mischer unter Verwendung von Unterabtastung von Signalen

    公开(公告)号：EP1176708A2

    公开(公告)日：2002-01-30

    申请号：EP01201318.1

    申请日：2001-04-10

    申请人： Texas Instruments Incorporated

    发明人： Staszewski, Robert B. ,  Leipold, Dirk

    IPC分类号： H03D7/00

    CPC分类号： H03D7/1441 ,  H03D7/125 ,  H03D7/1466 ,  H03D7/1475 ,  H04B1/28

    摘要： A multi-tap, digital-pulse-driven mixer advantageously avoids local oscillator (11) leakage by shifting the local oscillator frequency (F LO ) out of the received frequency band. Low noise figures are advantageously realized by the use of digital pulses (51, 52) as mixer drive signals (16).

    摘要翻译： 多抽头数字脉冲驱动混频器有利地通过将本地振荡器频率（FLO）移出接收频带来避免本地振荡器（11）的泄漏。 通过使用数字脉冲（51,52）作为混频器驱动信号（16），有利地实现了低噪声系数。