公开(公告)号：EP2989635A4

公开(公告)日：2018-04-25

申请号：EP14891595

申请日：2014-12-12

Applicant: VIA ALLIANCE SEMICONDUCTOR CO LTD

Inventor： HENRY G GLENN ,  JAIN DINESH K ,  GASKINS STEPHAN

IPC: G06F9/44 ,  G06F15/177 ,  G11C29/02 ,  H01L27/02

CPC classification number: G06F12/0893 ,  G06F1/3275 ,  G06F8/66 ,  G06F9/4403 ,  G06F12/0811 ,  G06F12/12 ,  G06F15/177 ,  G06F2212/222 ,  G06F2212/283 ,  G06F2212/601 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C2029/4402

Abstract: An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

公开(公告)号：EP2989553A4

公开(公告)日：2018-03-14

申请号：EP14891596

申请日：2014-12-12

Applicant: VIA ALLIANCE SEMICONDUCTOR CO LTD

Inventor： HENRY G GLENN ,  JAIN DINESH K ,  GASKINS STEPHAN

IPC: G06F9/44 ,  G06F15/177 ,  G11C29/02 ,  H01L27/02

CPC classification number: G06F12/0893 ,  G06F1/3275 ,  G06F8/66 ,  G06F9/4403 ,  G06F12/0811 ,  G06F12/12 ,  G06F15/177 ,  G06F2212/222 ,  G06F2212/283 ,  G06F2212/601 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C2029/4402

Abstract: An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

公开(公告)号：EP2989637A4

公开(公告)日：2018-04-25

申请号：EP14891594

申请日：2014-12-12

Applicant: VIA ALLIANCE SEMICONDUCTOR CO LTD

Inventor： HENRY G GLENN ,  JAIN DINESH K ,  GASKINS STEPHAN

IPC: G06F9/44 ,  G06F15/177 ,  G11C29/02 ,  H01L27/02

CPC classification number: G06F12/0893 ,  G06F1/3275 ,  G06F8/66 ,  G06F9/4403 ,  G06F12/0811 ,  G06F12/12 ,  G06F15/177 ,  G06F2212/222 ,  G06F2212/283 ,  G06F2212/601 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C2029/4402

Abstract: An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

公开(公告)号：EP3055769A4

公开(公告)日：2017-07-19

申请号：EP14891601

申请日：2014-12-14

Applicant: VIA ALLIANCE SEMICONDUCTOR CO LTD

Inventor： COL GERARD M ,  EDDY COLIN ,  HENRY G GLENN

IPC: G06F9/38

CPC classification number: G06F9/3855 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/38 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3861 ,  G06F12/0831 ,  G06F12/0875 ,  G06F12/1009

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include a system memory that is accessed via a memory bus, the system memory comprising one or more page tables, configured to store one or more mappings between virtual addresses and physical addresses.

Abstract translation: 一种包括第一和第二保留站的装置。 第一保留站分派加载微指令，并且在保持总线上指示加载微指令是否是指定的加载微指令以从除了核心上高速缓存存储器之外的指定资源中检索操作数。 第二保留站耦合到保持总线，并且在派发第一加载微指令之后的多个时钟周期之后，在其中分派一个或多个较新的微指令，这些微指令取决于加载微指令以执行，并且如果它指示为 所述加载微指令是指定的加载微指令的所述保持总线，所述第二保留站被配置为停止所述一个或更多个更新的微指令的分派，直到所述加载微指令已取回所述操作数为止。 资源包括经由存储器总线访问的系统存储器，系统存储器包括一个或多个页面表，其被配置为存储虚拟地址与物理地址之间的一个或多个映射。

公开(公告)号：EP3049956A4

公开(公告)日：2017-04-12

申请号：EP14891599

申请日：2014-12-14

Applicant: VIA ALLIANCE SEMICONDUCTOR CO LTD

Inventor： COL GERARD M ,  EDDY COLIN ,  HENRY G GLENN

IPC: G06F15/163

CPC classification number: G06F9/226 ,  G06F1/3243 ,  G06F9/30043 ,  G06F9/3836 ,  G06F12/0875 ,  G06F2212/452

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an input/output (I/O) unit, configured to perform I/O operations via an I/O bus coupling an out-of-order processor to I/O resources.

Abstract translation: 一种包括第一和第二保留站的装置。 第一保留站调度负载微指令，并且如果负载微指令是指定的从指定的资源而不是内核高速缓冲存储器检索操作数的指定负载微指令，则指示保持总线。 第二保留站耦合到保持总线，并且在分配第一加载微指令之后的数个时钟周期之后，发送依赖于负载微指令的一个或多个更小的微指令，并且如果在 所述保持总线，所述加载微指令是指定的加载微指令，所述第二保留站被配置为停止所述一个或多个较小的微指令的分派，直到所述加载微指令已经检索到所述操作数。 资源包括一个输入/输出（I / O）单元，配置为通过将乱序处理器耦合到I / O资源的I / O总线执行I / O操作。

公开(公告)号：EP3055768A4

公开(公告)日：2017-04-05

申请号：EP14891600

申请日：2014-12-14

Applicant: VIA ALLIANCE SEMICONDUCTOR CO LTD

Inventor： COL GERARD M ,  EDDY COLIN ,  HENRY G GLENN

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3861

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include system memory, coupled an out-of-order processor via a memory bus.

Abstract translation: 包括第一和第二保留站的装置。 第一保留站分派负载微指令，并在总线保持指示如果负载微指令是针对操作数从比核的高速缓冲存储器等规定的资源获取指定负载微指令。 第二保留站被耦合到保持总线，并调度一个或多个年轻的微指令。其中也取决于负载微指令供执行的数个时钟周期之后的第一负载微指令的调度之后，并且如果它被指示上 保持总线做的负载微指令是指定的负载微指令，所述第二保留站被配置直到负载微指令已经检索操作数失速的一个或多个微较新的指令调度。 所述资源包括系统存储器，其耦合到外的顺序处理器通过存储器总线。