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    CMOS OPERATIONAL AMPLIFIER WITH REDUCED POWER DISSIPATION.
    2.
    发明公开
    CMOS OPERATIONAL AMPLIFIER WITH REDUCED POWER DISSIPATION. 失效
    CMOS - 可降低功耗运算放大器。

    公开(公告)号：EP0037406A4

    公开(公告)日：1982-02-05

    申请号：EP80901914

    申请日：1981-04-08

    申请人： AMERICAN MICRO SYST

    发明人： HAQUE YUSUF AMINUL

    IPC分类号： H03F3/16 ,  H03F3/18 ,  H03F3/26 ,  H03F3/30 ,  H03F3/45

    CPC分类号： H03F3/45179 ,  H03F3/3001 ,  H03F3/3008 ,  H03F3/3025 ,  H03F3/45183 ,  H03F2203/30018 ,  H03F2203/30033 ,  H03F2203/30036 ,  H03F2203/45188 ,  H03F2203/45224 ,  H03F2203/45508 ,  H03F2203/45674 ,  H03F2203/45692

    摘要： Operational amplifier (10) comprised of MOSFET elements which provides for a variable drive for an output stage (18) that results in lower power dissipation and increased gain factor over comparable circuits using constant bias drive for the output stage. A bias section (14) comprised of complementary MOS elements (24, 26) is connected to a single MOSFET (40) that furnishes constant current to the signal input section of a differential amplifier section (20). The output of this differential amplifier is furnished by one path directly to one complementary MOSFET element (72) of a high impedance output stage and by another path to a level shift section (16) which provides an output to a second complementary MOSFET element (80) of the output stage. Thus, the circuit functions under class A-B operation at low power dissipation and provides high open loop gain. Additional embodiments of the invention utilize three MOSFET elements (104, 106, 108) in the level shift section or an additional output stage having an NPN transistor (120) in combination with an N channel MOSFET (122).

    TRI-WELL CMOS TECHNOLOGY.
    5.
    发明公开
    TRI-WELL CMOS TECHNOLOGY. 失效
    三个桶CMOS技术。

    公开(公告)号：EP0182876A4

    公开(公告)日：1986-11-10

    申请号：EP85902890

    申请日：1985-05-22

    申请人： AMERICAN MICRO SYST

    发明人： JOY RICHARD C ,  BATRA TARSAIM LAL

    IPC分类号： H01L21/76 ,  H01L21/033 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78

    CPC分类号： H01L27/0928 ,  H01L21/033 ,  H01L21/823892

    摘要： A semiconductor structure having at least three types of wells (65, 68, 71) which may be of different doping levels and methods of manufacturing such a structure. In one method, regions which will become active devices are protected with a nitride layer (62) as the associated well-regions (65, 68, 71) are implanted. In another method, previously implanted wells are covered with thick oxide (66, 69) which in combination with the nitride layer (62) provides automatic alignment of adjacent wells. In yet another method, implanted wells are covered with oxide (66) while a last well is implanted with this last well being defined by both thick oxide (66) and photoresist (67a). All methods avoid a masking step and avoid the need for aligning the edge of a later photoresist mask with the edge of an earlier photoresist mask. The structures formed by these methods may have heavily-doped P wells, heavily-doped N wells, and lightly-doped P or N wells, or both, for forming higher breakdown voltage devices on the same chip with lower breakdown voltage devices.

    Self adjusting sense amplifier clock delay circuit
    6.
    发明公开
    Self adjusting sense amplifier clock delay circuit 失效
    自适应传感放大器延迟电路

    公开(公告)号：EP0813206A3

    公开(公告)日：1998-12-23

    申请号：EP97108961

    申请日：1997-06-03

    申请人： WAFERSCALE INTEGRATION INC ,  AMERICAN MICRO SYST

    发明人： EITAN BOAZ ,  PETERSEN LARRY WILLIS ,  SLEZAK YARON

    IPC分类号： G11C11/41 ,  G11C7/06 ,  G11C8/18 ,  G11C16/06

    CPC分类号： G11C7/06 ,  G11C8/18

    摘要： A clock delay circuit for generating a delay for a sense amplifier release signal in an integrated circuit semiconductor memory device is disclosed. Rather than utilize traditional programmable capacitors that must be trimmed on a die by die basis, the novel clock delay circuit disclosed utilizes a small ROM, EPROM, EEPROM or FLASH array coupled to a bit line emulator to provide a clock delay matched to the larger main array. The size of the small memory array is on the order of 5 to 10 bit lines by 5 to 10 word lines. One cell within the small array is fixed to be continuously selected. The selected cell is coupled to the clock delay node along with the bit line emulator. The bit line emulator models the capacitance of the actual bit line used in the main array. However, the circuit is constructed so that a much larger signal is generated by the delay circuit such that sense amplifiers detect the correct signal. The CMOS based clock delay circuit uses the emulated array to generate a delta or margin that accurately tracks the delays within the main array with variations in temperature, supply voltage and process.