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    Operational transconductance amplifier
    2.
    发明公开
    Operational transconductance amplifier 审中-公开
    Transkonduktanz-Operationsverstärker

    公开(公告)号：EP2330735A2

    公开(公告)日：2011-06-08

    申请号：EP11154277.5

    申请日：2009-07-17

    Applicant: PEREGRINE SEMICONDUCTOR CORPORATION

    Inventor： Kim, Tae Youn ,  Englekirk, Robert Mark ,  Kelly, Dylan J.

    IPC: H03F3/45

    CPC classification number: H03F1/26 ,  H02M3/07 ,  H03F3/45183 ,  H03F3/45237 ,  H03F3/45475 ,  H03F3/45659 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/474 ,  H03F2203/45138 ,  H03F2203/45188 ,  H03F2203/45366 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45471 ,  H03F2203/45642 ,  H03H11/245 ,  H03K17/145

    Abstract: An integrated operational transconductance amplifier, OTA, having a variable-ratio current mirror differential amplifier section including:
    having a differential pair of FETs including a transistor having a source coupled to a source of a second transistor and to an approximate current source, the two forming a differential input pair of FETs for the OTA, the corresponding drains of the input pair forming a pair of differential current branches;
    having an output voltage connection Vo coupled to one of the differential current branches; and
    having a variable ratio current mirror circuit (113,114,115), including:
    having a current sensing circuit (114) conducting current from one of the differential current branches that generates a current control voltage reflective of the quantity of current thus conducted;
    having a current mirror reflection circuit (115) that generates a current substantially reflective of the current control voltage in the other differential current branch; and
    having a circuit, proportionally controllable by a signal (CMCV) applied to a mirror ratio control node within the OTA, which aids either conducting current of the current sensing circuit, or producing current reflective of the current control voltage, such that
    a ratio between current conducted by the current sensing circuit and the current mirror reflection circuit is continuously variable over a range under control of the signal (CMCV) applied to the mirror ratio control node.

    Abstract translation: 一种具有可变比电流镜差分放大器部分的集成运算跨导放大器OTA，包括：具有包括耦合到第二晶体管的源极的源极和近似电流源的晶体管的差分对FET，所述两个形成 用于OTA的差分输入对FET，输入对的相应的漏极形成一对差分电流分支; 具有耦合到所述差分电流分支之一的输出电压连接Vo; 并具有可变比电流镜电路（113,114,115），其包括：具有电流检测电路（114），该电流检测电路（114）从所述差分电流分支之一导通电流，所述电流检测电路产生反映所传导的电流量的电流控制电压; 具有电流镜反射电路（115），其生成在另一个差动电流分支中基本反射电流控制电压的电流; 并且具有由施加到OTA内的镜面比例控制节点的信号（CMCV）成比例地控制的电路，其有助于电流感测电路的导通电流，或者产生反映电流控制电压的电流，使得 由电流感测电路和电流镜反射电路传导的电流在施加到镜面比率控制节点的信号（CMCV）的控制下在一个范围内连续变化。

    Charge pump with a plurality of transfer control switches
    9.
    发明公开
    Charge pump with a plurality of transfer control switches 审中-公开
    Ladungspumpe mit einem Mehrzahl vonÜbertragungssteuerschaltern

    公开(公告)号：EP2421132A2

    公开(公告)日：2012-02-22

    申请号：EP11154276.7

    申请日：2009-07-17

    Applicant: PEREGRINE SEMICONDUCTOR CORPORATION

    Inventor： Kim, Tae Youn ,  Englekirk, Robert Mark ,  Kelly, Dylan J.

    IPC: H02M3/07

    CPC classification number: H03F1/26 ,  H02M3/07 ,  H03F3/45183 ,  H03F3/45237 ,  H03F3/45475 ,  H03F3/45659 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/474 ,  H03F2203/45138 ,  H03F2203/45188 ,  H03F2203/45366 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45471 ,  H03F2203/45642 ,  H03H11/245 ,  H03K17/145

    Abstract: A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an "active bias resistor" circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A threshold voltage bias voltage generation circuit may A charge pump for the bias generation may include a regulating feedback loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.

    Abstract translation: 由有助于低噪声和/或高效率偏置的许多特征的任何一个或任何实际组合限定的偏置产生方法或装置，包括：具有电荷泵控制时钟输出，其波形具有有限的谐波含量或失真，与 正弦波 具有环形振荡器以产生电荷泵时钟，该时钟包括由共源共栅器件限制的反相器电流，并实现基本的轨到轨输出幅度; 具有可选择的启动和/或相位锁定特征的差分环形振荡器，以产生适当匹配且具有适当相位的两相输出; 具有产生电荷泵时钟的小于五级的环形振荡器; 将时钟输出电容耦合到一些或全部电荷转移电容器开关; 通过仅在出现在端子之间的波形的部分期间在输出端之间传导的“有源偏置电阻器”电路将与电容耦合到驱动信号的FET偏压到偏置电压，和/或其中产生偏置电压 通过在所述波形的周期切换小电容。 阈值电压偏置电压产生电路可以用于偏置产生的电荷泵可以包括也适用于其他用途的OTA的调节反馈回路，OTA具有控制差分放大器中的电流镜像比的比率控制输入 并且可选地具有包括由第二差分放大器产生的反相输出的差分输出，其可选地包括由相同比例控制输入控制的可变比率电流镜。 因此，比率控制输入可以控制OTA的差分输出的共模电压。 围绕OTA的控制回路可以被配置为控制一个或多个可变比电流镜的比率，其可以特别地控制输出共模电压，并且可以控制它，使得反相输出电平跟踪非反相输出电平 使放大器充当高增益积分器。

    Signal amplifying circuit
    10.
    发明公开
    Signal amplifying circuit 审中-公开
    Signalverstärkerschaltung

    公开(公告)号：EP1045516A3

    公开(公告)日：2005-10-19

    申请号：EP00200946.2

    申请日：2000-03-15

    Applicant: Delphi Technologies, Inc.

    Inventor： Zarabadi, Seyed

    IPC: H03F3/45

    CPC classification number: H03F3/45179 ,  H03F3/45717 ,  H03F2203/45068 ,  H03F2203/45074 ,  H03F2203/45076 ,  H03F2203/45078 ,  H03F2203/45081 ,  H03F2203/45188 ,  H03F2203/45212 ,  H03F2203/45508

    Abstract: A signal amplifying circuit (24) includes level shifting input circuits (D1-D4) permitting input common-mode voltages (VIN1 and VIN2) of an amplifier and fault detection circuit (50) to vary between preset limits. The sense amplifier circuit (24) includes a DC offset buffer circuit (52) operable to receive an analog DC offset compensation signal and provide this signal to an input of the amplifier and fault detection circuit (50). The buffered DC offset compensation signal provided to the amplifier and fault detection circuit (50) is operable to reduce an aggregate DC offset voltage attributable to signal amplifying circuit (24) to a desired DC offset level. The amplifier and fault detection circuit (50) also includes a fault detection function whereby an output (VSENSE) of the amplifier circuit (50) is forced to a predetermined output state if either, or both, of the inputs (VIN1 and VIN2) of the sense amplifier circuit (24) are unconnected; i.e., floating. The output (VSENSE) of the amplifier and fault detection circuit (50) is provided to an output buffer circuit (54) operable to modulate the load current supplied to an output (VOUT1, VOUT2) thereof as a function of a difference between the amplifier output signal (VSENSE) and the output buffer output signal (VOUT1).

    Abstract translation: 信号放大电路（24）包括允许放大器和故障检测电路（50）的输入共模电压（VIN1和VIN2）在预设极限之间变化的电平移位输入电路（D1-D4）。 读出放大器电路（24）包括DC偏移缓冲电路（52），可操作以接收模拟DC偏移补偿信号，并将该信号提供给放大器和故障检测电路（50）的输入端。 提供给放大器和故障检测电路（50）的缓冲DC偏移补偿信号可操作以将归因于信号放大电路（24）的总的DC偏移电压减小到期望的DC偏移电平。 放大器和故障检测电路（50）还包括故障检测功能，由此如果放大器电路（50）的输入（VIN1和VIN2）的输入（VIN1和VIN2）中的任一个或两者被强制为预定的输出状态 感测放大器电路（24）不连接; 即浮动。 放大器和故障检测电路（50）的输出（VSENSE）被提供给输出缓冲器电路（54），该输出缓冲器电路（54）可用于调制提供给输出（VOUT1，VOUT2）的负载电流作为放大器 输出信号（VSENSE）和输出缓冲器输出信号（VOUT1）。

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