公开(公告)号：EP3072055A1

公开(公告)日：2016-09-28

申请号：EP14809196.0

申请日：2014-11-18

申请人： Microsoft Technology Licensing, LLC

发明人： QUACH, Nhon ,  AU, Stephen Z. ,  ZOU, Thomas ,  SHARPE, Tracy

IPC分类号： G06F13/40 ,  G06F13/24 ,  G06F13/28

CPC分类号： G06F13/32 ,  G06F13/24 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4027 ,  G06F2213/0026 ,  G06F2213/0038

摘要： One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA® bus. The interconnect chip may communicate with the IO device via the AMBA® bus in an AMBA® compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA® bus, receiving a response from the IO device over the AMBA® bus, and sending over the AMBA® bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.

摘要翻译： 一种公开的计算系统包括x86处理器，存储器，PCIe根复合（RC），PCIe总线和具有通过PCIe链路连接到PCIe RC的PCIe端点（EP）的互连芯片，PCIe EP 连接到AMBA®总线。 互连芯片可以通过AMBA®总线以符合AMBA的方式与IO设备进行通信，并以PCIe兼容方式与主机系统进行通信。 该通信可以包括从处理器接收命令，通过AMBA总线向IO设备发送命令，通过AMBA总线接收来自IO设备的响应，以及通过AMBA®总线和PCIe链路发送一个或 更多DMA操作到内存。 进一步的通信可以包括根据PCIe排序规则向主机系统的处理器发送IOAPIC中断。

公开(公告)号：EP3020178A1

公开(公告)日：2016-05-18

申请号：EP13889335.9

申请日：2013-07-09

申请人： Huazhong University of Science and Technology

发明人： JIN, Hai ,  DUAN, Pei ,  ZOU, Deqing

IPC分类号： H04L29/08

CPC分类号： G06F13/32 ,  G06F9/45533 ,  G06F11/3048 ,  G06F11/3068 ,  G06F13/14 ,  G06F2009/4557 ,  H04L63/08 ,  H04L69/08 ,  H04L69/16

摘要： To provide access to USB devices coupled to a client computing device for a user of virtual machine executing on a server, the server, in some examples, may be configured to pack USB request blocks into IP data packets and transmit the IP data packets over a network. Responsive to receiving the IP data packets, the client computing device may extract the USB request blocks from the IP data packets and provide the access to the USB devices for the virtual machine user.

摘要翻译： 为了提供访问耦合到用于在服务器上执行的虚拟机的用户的客户端计算设备的USB设备，在一些示例中，服务器可以被配置为将USB请求块打包成IP数据分组，并通过一个 网络。 响应于接收IP数据分组，客户端计算设备可以从IP数据分组中提取USB请求块，并为虚拟机用户提供对USB设备的访问。

公开(公告)号：EP2876559A1

公开(公告)日：2015-05-27

申请号：EP14197840.3

申请日：2011-01-26

申请人： Mitsubishi Electric Corporation

发明人： Nakata, Masanori ,  Kushiro, Noriyuki ,  Ito, Yoshiaki ,  Koizumi, Yoshiaki

IPC分类号： G06F13/28

CPC分类号： G06F13/34 ,  G06F12/00 ,  G06F13/28 ,  G06F13/32

摘要： A data reading device, characterized by comprising: a CPU (10); a first DMA controller (41); a second DMA controller (42); an external memory (51); an external memory interface (70); a first internal memory (31); and a second internal memory (32), wherein
the CPU (10) stores in the first internal memory (31) a given number of sets of command parameters comprising a reading start address from which reading starts and the size of data to be read in a single reading operation;
the first DMA controller (41) acquires a set of command parameters from the first internal memory (31) in sequence, and instructs the external memory interface (70) to execute the reading operation based on the set of command parameters;
the external memory interface (70) transfers the data read from the external memory (51) during the reading operation to the second DMA controller (42);
the second DMA controller (42) writes the data transferred from the external memory interface (70) in the second internal memory (32) in sequence, determines whether the transferred data match data specified by the CPU (10) in advance, and if these data match with each other, outputs a given interrupt signal indicating that the processing of the first and second DMA controllers (41, 42) ends; and
the CPU (10) accesses the second internal memory (32) and searches for the specified data when the interrupt signal is output.

摘要翻译： 一种数据读取装置，其特征在于包括：CPU（10）; 第一DMA控制器（41）; 第二DMA控制器（42）; 外部存储器（51）; 外部存储器接口（70）; 第一内部存储器（31）; 和第二内部存储器（32），其中所述CPU（10）在所述第一内部存储器（31）中存储给定数量的命令参数集合，所述命令参数组包括从其开始读取的读取开始地址和要读取的数据的大小 单次阅读操作; 第一DMA控制器（41）依次从第一内部存储器（31）获取一组命令参数，并且指示外部存储器接口（70）基于该组命令参数执行读取操作; 外部存储器接口（70）在读取操作期间将从外部存储器（51）读取的数据传送到第二DMA控制器（42）; 第二DMA控制器（42）依次将从外部存储器接口（70）传送的数据写入第二内部存储器（32）中，预先确定所传送的数据是否与CPU（10）指定的数据匹配， 数据彼此匹配，输出指示第一和第二DMA控制器（41,42）的处理结束的给定中断信号; 并且当输出中断信号时，CPU（10）访问第二内部存储器（32）并搜索指定的数据。

公开(公告)号：EP2838017A2

公开(公告)日：2015-02-18

申请号：EP14275158.5

申请日：2014-07-25

申请人： Sony Computer Entertainment Europe Ltd.

发明人： Brown, Neil Jonathan ,  Rogers, Phillip

IPC分类号： G06F9/44 ,  G06F3/14 ,  G09G5/39

CPC分类号： G06F5/16 ,  G06F1/1643 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G06F9/4418 ,  G06F9/461 ,  G06F9/4881 ,  G06F11/1438 ,  G06F11/1446 ,  G06F13/32 ,  G06F2003/0691 ,  G09G5/39

摘要： Data processing apparatus connectable to an associated display comprises a processor having an internal state dependent upon execution of application program code by the processor, the processor being operable to generate display data relating to images to be displayed using the associated display in response to the execution of the program code and to buffer display data relating to a most recent period of execution of a currently executing application; a non-volatile data storage arrangement operable to store program code for one or more applications; a random access memory operable to store temporary data relating to a current operational state of program execution while the processor is executing the program code for the currently executing application; a non-volatile suspend data memory; and a data transfer controller operable, in response to a suspend instruction, to transfer data from the random access memory relating to the currently executing application, data relating to a current internal state of the processor and the buffered display data to the suspend data memory, and operable, in response to a resume instruction, to transfer data from the suspend data memory to the random access memory and to the processor so as to recreate the state of execution of an application at the time that the suspend instruction was executed, and to retrieve the display data relating to the resumed application from the suspend data memory, the processor causing the display to display information based on the retrieved display data while the resume instruction is being completed.

摘要翻译： 可连接到相关联的显示器的数据处理设备包括处理器，其具有取决于处理器执行应用程序代码的内部状态，所述处理器可操作以响应于所述处理器的执行而生成与要显示的图像相关的显示数据 所述程序代码和用于缓冲与当前执行的应用程序的最近执行周期有关的显示数据; 非易失性数据存储装置，其可操作以存储用于一个或多个应用的​​程序代码; 随机存取存储器，用于在处理器正在执行当前执行的应用程序的程序代码时存储与程序执行的当前操作状态有关的临时数据; 非易失性挂起数据存储器; 以及数据传输控制器，其可响应于暂停指令，将与当前执行的应用有关的随机存取存储器中的数据与处理器的当前内部状态相关的数据和缓冲的显示数据传送到暂停数据存储器， 并且响应于恢复指令，可以将数据从挂起数据存储器传送到随机存取存储器和处理器，以便在执行挂起指令时重新创建应用程序的执行状态，并且 从暂停数据存储器检索与恢复的应用有关的显示数据，使得显示器的处理器在恢复指令完成时基于所检索的显示数据显示信息。

公开(公告)号：EP2657847A1

公开(公告)日：2013-10-30

申请号：EP10859818.6

申请日：2010-11-15

申请人： Fujitsu Limited

发明人： YAMASHITA, Koichiro ,  YAMAUCHI, Hiromasa ,  SUZUKI, Takahisa ,  KURIHARA, Koji ,  HAYAKAWA, Fumihiko

IPC分类号： G06F12/08 ,  G06F1/32 ,  G06F13/36

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G06F1/3237 ,  G06F13/1668 ,  G06F13/32 ,  G06F13/364 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14

摘要： Access contention for a shared resource (106) is resolved while suppressing power consumption in an information processing system (100). A bus controller (108) using a cache miss detecting unit (119), detects first information that indicates with respect to a CPU (101) and a CPU (102), a cache hit or a cache miss. The bus controller (108) using a high-speed I/O detecting unit (120), detects second information that indicates an activated state or a non-activated state of a DMA controller (103) and a DMA controller (104). The bus controller (108) using a generating unit (123), generates a setting signal based on the first information and the second information.

摘要翻译： 在消除信息处理系统（100）中的功率消耗的同时解决共享资源（106）的访问争用。 使用高速缓存未命中检测单元（119）的总线控制器（108）检测关于CPU（101）和CPU（102）指示的第一信息，高速缓存命中或高速缓存未命中。 使用高速I / O检测单元（120）的总线控制器（108）检测指示DMA控制器（103）和DMA控制器（104）的激活状态或非激活状态的第二信息。 使用生成单元（123）的总线控制器（108）根据第一信息和第二信息生成设定信号。

公开(公告)号：EP2194460A2

公开(公告)日：2010-06-09

申请号：EP09177809.2

申请日：2009-12-03

申请人： Sony Corporation

发明人： Kosaka, Hideo

IPC分类号： G06F13/32

CPC分类号： G06F13/4282 ,  G06F13/24 ,  G06F13/32 ,  H04B5/02 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D70/166 ,  Y02D70/42

摘要： An information-processing method performed in an information-processing apparatus, the information-processing apparatus (32) performing wireless communication with a first apparatus (11) and wire communication with a second apparatus (34), the information-processing method including the steps of:
transmitting an interrupt signal (IRQ) to the second apparatus (34) by using the wire communication when data is received from the first apparatus (11);
receiving, by using the wire communication, a clock signal (CLK) from the second apparatus (34) which receives the interrupt signal (IRQ); and
transmitting and receiving, by using the wire communication, data between the information-processing apparatus (32) and the second apparatus (34).

摘要翻译： 一种在信息处理设备中执行的信息处理方法，信息处理设备（32）执行与第一设备（11）的无线通信并且与第二设备（34）进行有线通信，所述信息处理方法包括步骤 ：当从第一装置（11）接收到数据时，通过使用有线通信将中断信号（IRQ）发送到第二装置（34）; 通过使用有线通信从接收中断信号（IRQ）的第二装置（34）接收时钟信号（CLK）; 以及通过使用有线通信在信息处理设备（32）和第二装置（34）之间发送和接收数据。

公开(公告)号：EP1499983B1

公开(公告)日：2006-03-29

申请号：EP03717304.4

申请日：2003-04-15

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： TUPPA, Walter

IPC分类号： G06F13/32

CPC分类号： G06F13/32 ,  Y02D10/14

摘要： The invention relates to a multiprocessor system, which comprises memory elements (M), input/output units (I/O) and a central bus system (CB), whereby the input/output units access the memory elements via the central bus system, using direct memory access. Said system is equipped with a bus observation element (BS), which during the read/write access by an input/output unit to a memory element via the central bus system monitors and evaluates the memory addresses that have been generated by the input/output unit and uses said addresses to generate interrupts in individual processors. This allows the computing capacity to be increased during the parallel processing of tasks.

公开(公告)号：EP1434138B1

公开(公告)日：2005-11-09

申请号：EP02293246.1

申请日：2002-12-26

申请人： ALCATEL

发明人： Geens, Ronald Maria Albert ,  Vogel, Luk

IPC分类号： G06F13/42

CPC分类号： G06F13/32 ,  G06F12/0623 ,  G06F12/08

公开(公告)号：EP0428330A3

公开(公告)日：1992-11-04

申请号：EP90312210.9

申请日：1990-11-08

申请人： International Business Machines Corporation

发明人： Garcia, Serafin Jose Eleazer, Jr. ,  Chisholm, Douglas Roderick ,  Kalman, Dean Alan ,  Padgett, Russell Stephen ,  Yoder, Robert Dean

IPC分类号： G06F13/30 ,  G06F13/32

CPC分类号： G06F13/32

摘要： A plurality of specialized controllers, e.g. 202, 204 & 206, each one adapted to control a particular type of data transfer operation, control the flow of data between a system bus 104 and a local bus 106 on a computer adapter card 102. When the Direct Memory Access DMA controller 202 is controlling a DMA operation on the local bus, certain other controllers 204 & 206 can break-in to the current DMA operation, temporarily halting the DMA operation until the other controller has completed its data transfer operation. To break-in to a DMA operation, handshaking signals between the DMA controller and the local bus interface circuit 212 are temporarily blocked by blocking signals from a break-in logic circuit 210 . The break-in circuit includes a four-state state machine to block the handshaking signals at the appropriate times, and to signal the interrupting controller to begin its data transfer operation. When breaking-in to a DMA operation in this manner, the operation of the DMA controller is not altered; instead, to the DMA controller, it appears that the local bus interface circuit is merely slow to respond with its acknowledge handshake.

公开(公告)号：EP0317567A4

公开(公告)日：1991-03-13

申请号：EP87905044

申请日：1987-07-14

申请人： COMMODORE-AMIGA, INC.

发明人： KELLER, GLENN ,  MINER, JAY, G.

IPC分类号： G06F13/12 ,  G06F3/06 ,  G06F3/16 ,  G06F13/32 ,  G06F13/38 ,  G06F3/00 ,  G06F9/00 ,  G06F13/00 ,  G06F13/14 ,  G06F13/40

CPC分类号： G06F3/0601 ,  G06F3/162 ,  G06F13/32 ,  G06F13/38 ,  G06F2003/0692

摘要： Control and interface circuitry for right and left audio channels (29, 33, 37, 41; 31, 35, 39, 43), a disk storage medium (53, 55, 57, 61), a UART (81, 79, 73, 77, 69) and up to four potentiometer ports (97, 95, 93, 83). The design includes a separate interrupt priority control and status circuit (25, 27) for channel control communication with the personal computer microprocessor. Much of the burden associated with personal computer microprocessor peripheral control is alleviated by employing a separate address and data bus (15; 23) and direct memory access for some peripheral control circuits. In operation, each control circuit includes a data register (29, 31, 53, 81, 97) for the reception and transmission of data via the data bus (23); a register address decoder (17) decodes device addresses appearing on the address bus (15), enabling, via separate enabling lines (99), the corresponding devices for the reception of data. Audio and disk channel control logic (33, 35, 55) access memory directly by sending requests to a DMA request logic parallel - to - serial multiplexor (49).