公开(公告)号：EP1844547A1

公开(公告)日：2007-10-17

申请号：EP06704552.6

申请日：2006-01-16

申请人： NXP B.V.

发明人： MOONEN, Oswald Josef ,  VLEMMINGS, Marc Lambertus Johannes ,  NEELEN, Arnold Hendrik

IPC分类号： H03F3/45 ,  H03D7/14

CPC分类号： H03F3/45 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0043 ,  H03F1/3211 ,  H03F3/45098 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/513 ,  H03F2203/45458 ,  H03F2203/45472 ,  H03F2203/45702

摘要： A low-power high dynamic range RF input stage (200) with a noiseless degeneration component, such as a capacitor (201), is provided. High dynamic range means a combination of low noise contribution by the stage (200) and a low level of intermodulation products occurring especially at high input levels. Low power means that the power consumption of a conventional input stage is about 5 times higher than the power consumption of the stage according to the invention, for the same noise, gain and distortion level. This new stage can be used in amplifiers, but also in the lower stage of double balanced mixers (300-400) commonly used in RF receivers, examples of which are applications, are provided.

公开(公告)号：EP0358266B1

公开(公告)日：1996-04-10

申请号：EP89202209.6

申请日：1989-09-01

申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

发明人： Hughes, John Barry

IPC分类号： H03F3/45

CPC分类号： H03F3/45278 ,  H03F3/45381 ,  H03F2203/45472 ,  H03F2203/45476 ,  H03F2203/45496

公开(公告)号：EP0358266A2

公开(公告)日：1990-03-14

申请号：EP89202209.6

申请日：1989-09-01

申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

发明人： Hughes, John Barry

IPC分类号： H03F3/45

CPC分类号： H03F3/45278 ,  H03F3/45381 ,  H03F2203/45472 ,  H03F2203/45476 ,  H03F2203/45496

摘要： An operational amplifier circuit comprises a differential input stage (22) and an output transistor (N3) driven by an output (24) of the differential input stage. Means (N4, P3, P5) for generating a bias current for the differential input stage are constructed so that in operation the bias current is in a predetermined proportion to the current flowing in the output transistor (N3) and is substantially independent of the impedance (Z) of any load driven by the output transistor, thereby eliminating a systematic offset error. The means for generating the bias current may include a further transistor (N4) driven by the output of the differential input stage.

摘要翻译： 运算放大器电路包括差分输入级（22）和由差分输入级的输出（24）驱动的输出晶体管（N3）。 用于产生用于差分输入级的偏置电流的装置（N4，P3，P5）被构造成使得在操作中偏置电流与在输出晶体管（N3）中流动的电流成预定比例，并且基本上与阻抗 （Z）由输出晶体管驱动的任何负载，从而消除系统偏移误差。 用于产生偏置电流的装置可以包括由差分输入级的输出驱动的另一个晶体管（N4）。

公开(公告)号：EP3193446A1

公开(公告)日：2017-07-19

申请号：EP17150596.9

申请日：2017-01-08

申请人： Melexis Technologies SA

发明人： RAMAN, Johan ,  ROMBOUTS, Pieter

IPC分类号： H03F3/393 ,  H03F3/45 ,  H03F3/00

CPC分类号： H03F3/45475 ,  G01C17/28 ,  G01D5/142 ,  G01R33/07 ,  H03F3/005 ,  H03F3/387 ,  H03F3/393 ,  H03F3/45098 ,  H03F3/45197 ,  H03F2200/129 ,  H03F2200/135 ,  H03F2200/156 ,  H03F2200/171 ,  H03F2200/261 ,  H03F2200/264 ,  H03F2200/27 ,  H03F2200/271 ,  H03F2200/294 ,  H03F2200/312 ,  H03F2200/321 ,  H03F2200/372 ,  H03F2200/375 ,  H03F2200/81 ,  H03F2203/45288 ,  H03F2203/45472 ,  H03F2203/45496 ,  H03F2203/45512 ,  H03F2203/45514 ,  H03F2203/45528 ,  H03F2203/45536 ,  H03F2203/45552 ,  H03F2203/45564 ,  H03F2203/45594 ,  H03F2203/45596

摘要： A semiconductor circuit (200) comprising an input block having a first chopper (CH1) providing a chopped voltage signal (Vin_ch), a first transconductance (G1) converting said chopped voltage signal into a chopped current signal (I_ch), a second chopper (CH2) providing a demodulated current signal (I_demod), a current integrator (CI1) having an integrating capacitor (Cint) providing a continuous-time signal (Vct), a first feedback path comprising: a sample-and-hold block and a first feedback block (G2), the first feedback path providing a proportional feedback signal (Vfb, Ifb) upstream of the current integrator (CI1). The amplification factor is at least 2. Charge stored on the integrating capacitor (Cint) at the beginning of a sample period is linearly removed during one single sampling period (Ts). Each chopper operates at a chopping frequency (fc). The sample-and-hold-block operates at a sampling frequency (fs) equal to an integer (N) times the chopping frequency (fc).

摘要翻译： 一种半导体电路（200），包括具有提供斩波电压信号（Vin_ch）的第一斩波器（CH1），将所述斩波电压信号转换成斩波电流信号（I_ch）的第一互导（G1），第二斩波器 CH2），提供解调电流信号（I_demod），具有提供连续时间信号（Vct）的积分电容器（Cint）的电流积分器（CI1），第一反馈路径包括：采样保持块和第一 反馈块（G2），第一反馈路径在电流积分器（CI1）的上游提供比例反馈信号（Vfb，Ifb）。 放大系数至少为2.在采样周期开始时存储在积分电容（Cint）上的电荷在单个采样周期（Ts）内线性移除。 每个斩波器以斩波频率（fc）运行。 采样保持块以等于斩波频率（fc）整数（N）的采样频率（fs）运行。

公开(公告)号：EP1844547B1

公开(公告)日：2015-01-14

申请号：EP06704552.6

申请日：2006-01-16

申请人： NXP B.V.

发明人： MOONEN, Oswald Josef ,  VLEMMINGS, Marc Lambertus Johannes ,  NEELEN, Arnold Hendrik

IPC分类号： H03F3/45 ,  H03D7/14

CPC分类号： H03F3/45 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0043 ,  H03F1/3211 ,  H03F3/45098 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/513 ,  H03F2203/45458 ,  H03F2203/45472 ,  H03F2203/45702

公开(公告)号：EP0296131B1

公开(公告)日：1992-04-15

申请号：EP88850158.2

申请日：1988-05-09

申请人： TELEFONAKTIEBOLAGET L M ERICSSON

发明人： Mäder, Heinz Bernhard

IPC分类号： H03H11/04

CPC分类号： H03H11/04 ,  H03F3/45098 ,  H03F2203/45388 ,  H03F2203/45472

公开(公告)号：EP0358266A3

公开(公告)日：1990-12-27

申请号：EP89202209.6

申请日：1989-09-01

申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

发明人： Hughes, John Barry

IPC分类号： H03F3/45

CPC分类号： H03F3/45278 ,  H03F3/45381 ,  H03F2203/45472 ,  H03F2203/45476 ,  H03F2203/45496

摘要： An operational amplifier circuit comprises a differential input stage (22) and an output transistor (N3) driven by an output (24) of the differential input stage. Means (N4, P3, P5) for generating a bias current for the differential input stage are constructed so that in operation the bias current is in a predetermined proportion to the current flowing in the output transistor (N3) and is substantially independent of the impedance (Z) of any load driven by the output transistor, thereby eliminating a systematic offset error. The means for generating the bias current may include a further transistor (N4) driven by the output of the differential input stage.

公开(公告)号：EP0296131A1

公开(公告)日：1988-12-21

申请号：EP88850158.2

申请日：1988-05-09

申请人： TELEFONAKTIEBOLAGET L M ERICSSON

发明人： Mäder, Heinz Bernhard

IPC分类号： H03H11/04

CPC分类号： H03H11/04 ,  H03F3/45098 ,  H03F2203/45388 ,  H03F2203/45472

摘要： The invention can be related to the technical field of implementation and control of electrically controllable active filters.
In accordance with the invention filters are controlled and implemented with the aid of a differential gain stage. Said stage includes pairs of like amplifica­tion components (Q I11 and Q I21 , Q I12 and Q I22 , Q I13 and Q I23 ), and groups of series-connected diode components as well as at least one current generator (Q1, Q2, Q3). The forward voltage drop of the diode components has the same current responsiveness as the base-emitter voltage of the amplification com­ponents. A filter of the first order includes a differential gain stage with a capacitive component (C) connected across the output of said stage or to its amplification components. A filter of the second order can include two differential gain stages, each with its capacitive component (C1, C2) in circuit. An oscillator for controlling filters can comprise three series-connected low-­pass filters each including its differential gain stage.

摘要翻译： 本发明可以与电可控有源滤波器的实现和控制技术领域有关。 根据本发明，借助于差分增益级来控制和实现滤波器。 所述级包括一对类似的放大组件（QI11和QI21，QI12和QI22，QI13和QI23）以及串联二极管组件组以及至少一个电流发生器（Q1，Q2，Q3）。 二极管组件的正向压降具有与放大组件的基极 - 发射极电压相同的电流响应性。 第一级的滤波器包括具有连接在所述级的输出端或其放大部件上的电容分量（C）的差分增益级。 第二级的滤波器可以包括两个差分增益级，每个具有电路中的电容分量（C1，C2）。 用于控制滤波器的振荡器可以包括三个串联连接的低通滤波器，每个包括其差分增益级。