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    A PROGRAMMABLE-GAIN AMPLIFIER, CORRESPONDING DEVICE AND METHOD
    2.
    发明公开
    A PROGRAMMABLE-GAIN AMPLIFIER, CORRESPONDING DEVICE AND METHOD 有权
    一种可编程增益放大器，相应的装置和方法

    公开(公告)号：EP3185415A1

    公开(公告)日：2017-06-28

    申请号：EP16172129.5

    申请日：2016-05-31

    申请人： STMicroelectronics S.r.l.

    发明人： SAUTTO, Marco ,  QUAGLIA, Fabio ,  RICOTTI, Giulio ,  MAZZANTI, Andrea

    IPC分类号： H03F3/00 ,  H03F3/45

    CPC分类号： H03G1/0094 ,  H03F3/005 ,  H03F3/2175 ,  H03F3/45 ,  H03F3/45264 ,  H03F2200/312 ,  H03F2203/45288

    摘要： In an embodiment, a programmable-gain amplifier includes: two complementary cross-coupled transistor (e.g. MOS) pairs (M n-a , M n-b ; M p-a , M p-b ) mutually coupled with each transistor in one pair (M n-a resp. M n-b ) having a current flow path cascaded with a current flow path of a respective one of the transistors in the other pair (M p-a resp. M p-b ) to provide first (A) and second (B) coupling points between said complementary cross-coupled transistor pairs (M n-a , M n-b ; M p-a , M p-b ); first (C a ) and second (C b ) sampling capacitors set between the first (A) and second (B) coupling points, respectively, and ground; first (10) and second (12) input stages having input terminals for receiving input signals (V in- , V in+ ) for sampling by the first (C a ) and second (C b ) sampling capacitors. Switching means (201 to 206; 301, 302) are provided for:
    - i) coupling the first (10) and second (12) input stages to the first (C a ) and second (C b ) sampling capacitors, whereby the input signals (V in- , V in+ ) are sampled as sampled signals (V out+ , V out- ) on said first (C a ) and second (C b ) sampling capacitors, and
    - ii) energizing (V dd ) the complementary cross-coupled transistor pairs (M n-a , M n-b ; M p-a , M p-b ) whereby the signals (V out+ , V out- ) sampled on the first (C a ) and second (C b ) sampling capacitors undergo negative resistance regeneration growing exponentially over time, thereby providing an exponential amplifier gain.

    摘要翻译： 在一个实施例中，可编程增益放大器包括：与一对中的每个晶体管（Mn-a，Mn-b; Mp-a， （Mp-a或Mp-b）中的相应一个晶体管的电流流动路径级联的电流流动路径以提供第一（A）和第二（B） 所述互补交叉耦合晶体管对（Mn-a，Mn-b; Mp-a，Mp-b）之间的耦合点; 分别在第一（A）和第二（B）耦合点之间设置的第一（Ca）和第二（Cb）采样电容器以及地; 第一（10）和第二（12）输入级具有用于接收输入信号（Vin-，Vin +）以供第一（Ca）和第二（Cb）采样电容器采样的输入端。 提供切换装置（201至206; 301,302）用于：i）将第一（10）和第二（12）输入级耦合至第一（Ca）和第二（Cb）采样电容器，由此输入信号 Vin和Vin +）在所述第一（Ca）和第二（Cb）采样电容器上被采样为采样信号（Vout +，Vout-），以及-ii）激励（Vdd）互补交叉耦合晶体管对（Mn- 由此在第一（Ca）和第二（Cb）采样电容器上采样的信号（Vout +，Vout-）经历随时间呈指数增长的负电阻再生，由此提供指数放大器增益 。

    A PROGRAMMABLE-GAIN AMPLIFIER, CORRESPONDING DEVICE AND METHOD
    4.
    发明授权
    A PROGRAMMABLE-GAIN AMPLIFIER, CORRESPONDING DEVICE AND METHOD 有权

    公开(公告)号：EP3185415B1

    公开(公告)日：2018-07-25

    申请号：EP16172129.5

    申请日：2016-05-31

    申请人： STMicroelectronics S.r.l.

    发明人： SAUTTO, Marco ,  QUAGLIA, Fabio ,  RICOTTI, Giulio ,  MAZZANTI, Andrea

    IPC分类号： H03F3/00 ,  H03F3/45 ,  H03F3/217 ,  H03G1/00

    CPC分类号： H03G1/0094 ,  H03F3/005 ,  H03F3/2175 ,  H03F3/45 ,  H03F3/45264 ,  H03F2200/312 ,  H03F2203/45288

    摘要： In an embodiment, a programmable-gain amplifier includes: two complementary cross-coupled transistor (e.g. MOS) pairs (M n-a , M n-b ; M p-a , M p-b ) mutually coupled with each transistor in one pair (M n-a resp. M n-b ) having a current flow path cascaded with a current flow path of a respective one of the transistors in the other pair (M p-a resp. M p-b ) to provide first (A) and second (B) coupling points between said complementary cross-coupled transistor pairs (M n-a , M n-b ; M p-a , M p-b ); first (C a ) and second (C b ) sampling capacitors set between the first (A) and second (B) coupling points, respectively, and ground; first (10) and second (12) input stages having input terminals for receiving input signals (V in- , V in+ ) for sampling by the first (C a ) and second (C b ) sampling capacitors. Switching means (201 to 206; 301, 302) are provided for: - i) coupling the first (10) and second (12) input stages to the first (C a ) and second (C b ) sampling capacitors, whereby the input signals (V in- , V in+ ) are sampled as sampled signals (V out+ , V out- ) on said first (C a ) and second (C b ) sampling capacitors, and - ii) energizing (V dd ) the complementary cross-coupled transistor pairs (M n-a , M n-b ; M p-a , M p-b ) whereby the signals (V out+ , V out- ) sampled on the first (C a ) and second (C b ) sampling capacitors undergo negative resistance regeneration growing exponentially over time, thereby providing an exponential amplifier gain.

    SWITCHED-CAPACITOR BUFFER AND RELATED METHODS
    7.
    发明公开
    SWITCHED-CAPACITOR BUFFER AND RELATED METHODS 审中-公开
    开关电容缓冲器及相关方法

    公开(公告)号：EP3244531A1

    公开(公告)日：2017-11-15

    申请号：EP17170013.1

    申请日：2017-05-08

    申请人： MediaTek Inc.

    发明人： AWAD, Ramy

    IPC分类号： H03F3/00 ,  H03F3/50 ,  H03F3/30

    CPC分类号： H02M3/07 ,  H03F3/005 ,  H03F3/301 ,  H03F3/3069 ,  H03F3/505 ,  H03F2200/219 ,  H03F2200/231 ,  H03F2200/252 ,  H03F2200/27 ,  H03F2200/297 ,  H03F2200/312 ,  H03F2200/396 ,  H03F2200/414 ,  H03F2200/417 ,  H03F2200/42 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/513 ,  H03F2200/69

    摘要： A line receiver (100) comprising a switched capacitor circuit (102) and a buffer (108) is described. The buffer (108) may be configured to receive, through the switched capacitor circuit (102), an analog signal. In response, the buffer (102) may provide an output signal to a load (110), such as an analog-to-digital converter. The switched capacitor circuit (102) may be controlled by a control circuitry (112), and may charge at least one capacitive element (106) to a desired reference voltage. The reference voltage may be selected so as to bias the buffer (108) with a desired DC current, and consequently, to provide a desired degree of linearity. The line receiver (100) may further comprise a bias circuit (300) configured to generate the reference voltage needed to bias the buffer (108) with the desired DC current.

    摘要翻译： 描述了包括开关电容器电路（102）和缓冲器（108）的线路接收器（100）。 缓冲器（108）可以被配置为通过开关电容器电路（102）接收模拟信号。 作为响应，缓冲器（102）可以将输出信号提供给负载（110），例如模数转换器。 开关电容器电路（102）可以由控制电路（112）控制，并且可以将至少一个电容元件（106）充电至期望的参考电压。 可以选择参考电压以便用期望的DC电流偏置缓冲器（108），并且因此提供期望的线性度。 线路接收器（100）还可以包括偏置电路（300），偏置电路（300）被配置为生成用于以期望的DC电流偏置缓冲器（108）所需的参考电压。