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14 条记录 (耗时 0.009 秒)

    IMPROVED FLOATING, BALANCED OUTPUT CIRCUIT
    1.
    发明公开
    IMPROVED FLOATING, BALANCED OUTPUT CIRCUIT 有权
    浮动不对称输出电路

    公开(公告)号：EP1238456A2

    公开(公告)日：2002-09-11

    申请号：EP00993061.1

    申请日：2000-11-07

    申请人： That Corporation

    发明人： HEBERT, Gary, K.

    IPC分类号： H03G1/00

    CPC分类号： H03F3/45506 ,  H03F3/45618 ,  H03F3/45991

    摘要： A floating, balanced output stage maintains control of the common-mode output current in both output legs even when the differential voltage output is clipped. The circuit includes a pair of transconductance amplifier section (gm1) for providing a differential pair of output currents in response to the input voltage (Vin); an intermediate section (2-5) connected so as to generate an intermediate differential output voltage (V1, V2), across two outputs of the intermediate section, in response to the pair of output currents of the first transconductance amplifier; an output section (R5-R8) for generating the differential output voltage (Vout+, Vout-) in response to the pair of voltages generated by the intermediate section; a differential feedback loop configuration (R3, R4) connected around the first transconductance amplifier and the intermediate section so as to provide differential negative feedback in response to the intermediate differential output voltage generated by the intermediate section; and a common-mode feedback loop comprising a second transconductance amplifier section (gm2) connected around the intermediate section so as to respectively add a pair of substantially matched output currents to the output currents of the first transconductance amplifier in response to the common-mode current.

    Differential amplifier having balanced output
    3.
    发明公开
    Differential amplifier having balanced output 失效
    差分放大器，平衡输出。

    公开(公告)号：EP0117625A1

    公开(公告)日：1984-09-05

    申请号：EP84300462.3

    申请日：1984-01-25

    申请人： HAZELTINE CORPORATION

    发明人： Hana, Thomas C. ,  Henrich, Kenneth J.

    IPC分类号： H03F1/32 ,  H03F3/45

    CPC分类号： H03F1/3211 ,  H03F3/45103 ,  H03F3/45609 ,  H03F3/45618

    摘要： A classical differential amplifier (100) provides output of unequal magnitude due to its emitter resistance being finite. In order to equalize its output, a voltage follower circuit (200, 300) is associated with each of the inputs of the differential amplifier. The output of each voltage follower circuit is converted to current (202, 302) and subtracted (400, 500) from one of the outputs of the differential amplifier. Subtracting the outputs results in a differential amplifier with both outputs being substantially equal.

    PRE-AMPLIFIER
    4.
    发明公开
    PRE-AMPLIFIER 失效
    前置放大器。

    公开(公告)号：EP0673563A1

    公开(公告)日：1995-09-27

    申请号：EP94903382.0

    申请日：1993-12-01

    申请人： KNOWLES ELECTRONICS, INC.

    发明人： FRENCH, John, S. ,  PETERS, Richard, W.

    IPC分类号： H03F1 ,  H03F3 ,  H04R19 ,  H04R25

    CPC分类号： H03F3/187 ,  H03F1/226 ,  H03F3/45085 ,  H03F3/45618 ,  H04R25/50

    摘要： A tiny, pre-amplifier for a small, low voltage, high impedance source (14), usually an electret microphone, exhibiting near unity gain, has an input cascode stage (16) connected to the microphone and a matched balancing cascode stage (19); both cascode stages are energized from the same power supply circuit (11). The two cascode stages supply intermediate signals to the input (17, 21) of a differential amplifier (18) to generate an output signal having a greatly reduced noise content, independent of power supply variations. The pre-amplifier is wholly integrateable, has low power drain, and fits into the microphone housing.

    Verstärkerschaltung mit einer symmetrisch aufgebauten Eingangsstufe
    6.
    发明公开
    Verstärkerschaltung mit einer symmetrisch aufgebauten Eingangsstufe 失效
    Verstärkerschaltungmit einer symmetricrisch aufgebauten Eingangsstufe。

    公开(公告)号：EP0080242A1

    公开(公告)日：1983-06-01

    申请号：EP82201475.9

    申请日：1982-11-19

    申请人： Philips Patentverwaltung GmbH ,  Philips Electronics N.V.

    发明人： Gottlieb, Detlef

    IPC分类号： H03F3/45 ,  H01L27/08

    CPC分类号： H03F3/45991 ,  H01L27/0825 ,  H03F3/45085 ,  H03F3/4517 ,  H03F3/45618 ,  H03F2203/45596 ,  H03F2203/45702

    摘要： Bei Verstärkern mit symmetrisch aufgebauter Differenzverstärker-Eingangsstufe kann durch einen Ruhestrom über einen mit einem der beiden Eingänge verbundenen Vorwiderstand (8) ein Eingangsspannungs-Offset auftreten. Dieser Eingangsspannungs-Offset kann, insbesondere bei integrierten Schaltungen, dadurch verringert bzw. kompensiert werden, daß ein Transistor des Zweiges der Differenzverstärker-Eingangsstufe, mit dem der Vorwiderstand verbunden ist, eine größere Emitterfläche erhält als der entsprechende Transistor des anderen Zweiges.

    摘要翻译： 在具有平衡差分放大器输入级的放大器中，通过连接到两个输入之一的偏置电阻（8）的静态电流可以产生输入电压偏移。 可以减小或补偿该输入电压偏移，特别是在集成电路中，为了提供偏置电阻器所连接的差分放大器输入级的支路的晶体管，具有比另一个分支的相应晶体管更大的发射极面积 。

    IMPROVED FLOATING, BALANCED OUTPUT CIRCUIT
    9.
    发明公开
    IMPROVED FLOATING, BALANCED OUTPUT CIRCUIT 有权
    浮动不对称输出电路

    公开(公告)号：EP1238456A4

    公开(公告)日：2004-12-22

    申请号：EP00993061

    申请日：2000-11-07

    申请人： THAT CORP

    发明人： HEBERT GARY K

    IPC分类号： H03F3/68 ,  H03F1/34 ,  H03F3/45 ,  H03K5/22

    CPC分类号： H03F3/45506 ,  H03F3/45618 ,  H03F3/45991

    摘要： A floating, balanced output stage maintains control of the common-mode output current in both output legs even when the differential voltage output is clipped. The circuit includes a pair of transconductance amplifier section (gm1) for providing a differential pair of output currents in response to the input voltage (Vin); an intermediate section (2-5) connected so as to generate an intermediate differential output voltage (V1, V2), across two outputs of the intermediate section, in response to the pair of output currents of the first transconductance amplifier; an output section (R5-R8) for generating the differential output voltage (Vout+, Vout-) in response to the pair of voltages generated by the intermediate section; a differential feedback loop configuration (R3, R4) connected around the first transconductance amplifier and the intermediate section so as to provide differential negative feedback in response to the intermediate differential output voltage generated by the intermediate section; and a common-mode feedback loop comprising a second transconductance amplifier section (gm2) connected around the intermediate section so as to respectively add a pair of substantially matched output currents to the output currents of the first transconductance amplifier in response to the common-mode current.

    Differential amplifier circuit with precision active load
    10.
    发明公开
    Differential amplifier circuit with precision active load 失效
    SchaltungsanordnungfüreinenDifferenzverstärkermitpräziseraktiver Last。

    公开(公告)号：EP0072082A1

    公开(公告)日：1983-02-16

    申请号：EP82301339.6

    申请日：1982-03-16

    申请人： PRECISION MONOLITHICS INC.

    发明人： Nishikawa, Yukio ,  Fukahori, Kiyoshi

    IPC分类号： H03F3/45

    CPC分类号： H03F3/343 ,  H03F3/45085 ,  H03F3/45618 ,  H03F2203/45654 ,  H03F2203/45674 ,  H03F2203/45676

    摘要： A differential amplifier circuit is provided with a precision action load consisting of primary and secondary transistor load circuits. The primary circuit (40, 46) provides primary load currents to the amplifier branches (2, 4) which are mutually unbalanced by an amount which is proportional to the inverse of the first and second power of transistor current gain, while the secondary circuit (54, 56) provides a balancing current to one of the amplifier branches which also has components proportional to the inverse of the first and second power of transistor current gain. The primary and secondary load circuits include junction transistors which are matched with each other and provide balanced multi-junction paths between the amplifier branches and a voltage supply (20), clamping the branch voltages in mutual balance. The resulting input voltage offset is reduced to a function of the inverse of the third power of transistor current gain, without sacrificing amplifier gain, bandwidth or simplicity.

    摘要翻译： 差分放大器电路具有由主晶体管负载电路和次级晶体管负载电路组成的精密作用负载。 主电路（40,46）向放大器分支（2,4）提供初级负载电流，这两个分支彼此不平衡的量与晶体管电流增益的第一和第二功率成反比，而次级电路 54,56）向一个放大器分支提供平衡电流，其中还具有与晶体管电流增益的第一和第二功率的倒数成比例的分量。 初级和次级负载电路包括彼此匹配的结型晶体管，并且在放大器支路之间提供平衡的多结路径和电压源（20），以相互平衡的方式钳位分支电压。 所产生的输入电压偏移减小到晶体管电流增益的第三功率的倒数的函数，而不会牺牲放大器增益，带宽或简单性。