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1.发明公开
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2.发明公开COMPLEX BANDPASS DELTA SIGMA AD MODULATOR AND DIGITAL RADIO RECEIVER 审中-公开KOMPLEXER BANDPASS-SIGMA-DELTA-AD-MODULATOR UND DIGITALERFUNKEMPFÄNGER
公开(公告)号：EP2405580A1
公开(公告)日：2012-01-11
申请号：EP10748653.2
申请日：2010-02-24
发明人： SAN Hao , KOBAYASHI Haruo
摘要： To provide a complex bandpass ΔΣAD modulator capable of suppressing the influence of an image component caused by a mismatch between I- and Q-channels on a signal component with low power consumption.
A complex bandpass ΔΣAD modulator 10 is configured by a subtraction unit 20, a complex bandpass filter 30, an addition unit 40, a noise extraction circuit unit 50, an ADC unit 60, and a DAC unit 70. The noise extraction circuit unit 50 extracts a quantized noise signal of the ADC unit 60 based on an input signal of the ADC unit 60 and an output signal of the DAC unit 70, delays the extracted quantized noise signal by one sample time, phase-rotates the delayed signal by a predetermined angle, and feeds back the rotated signal to the input side of the ADC unit 60. Thus, a complex bandpass ΔΣAD modulator capable of suppressing the influence of the image component caused by a mismatch between I- and Q-channels on the signal component with low power consumption is provided.摘要翻译： 提供能够以低功耗消除信号分量上由I-通道与Q通道之间的失配引起的图像成分影响的复合带通“AD AD调制器”。 复数带通“AD调制器10由减法单元20，复带通滤波器30，加法单元40，噪声提取电路单元50，ADC单元60和DAC单元70构成。噪声提取电路单元 50基于ADC单元60的输入信号和DAC单元70的输出信号提取ADC单元60的量化噪声信号，将提取的量化噪声信号延迟一个采样时间，将延迟信号相位旋转一个 并且将旋转的信号反馈到ADC单元60的输入侧。因此，能够抑制由I-和Q通道之间的失配引起的图像分量的影响的复带通“AD调制器 提供低功耗的信号分量。
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3.发明公开
公开(公告)号：EP1794889A1
公开(公告)日：2007-06-13
申请号：EP05792313.8
申请日：2005-09-19
申请人： Eads Telecom
发明人： ROBBE, Michel , DOUCET, Stéphane , GUEGNAUD, Hervé
IPC分类号： H03M3/00
摘要： In order to convert a complex analog signal into a complex digital signal in an analog-digital conversion device having two channels, I and Q respectively, in quadrature, each comprising an input and an associated output, each output being fed back onto said associated input so as to form a first and a second feedback loops each comprising a digital-analog converter, the device comprising a complex filter with a first stage and a last stage, after sampling (508), a signal integration is performed in a first stage (501) of the filter without introducing any substantial delay. Then, an integration is performed in the last stage (502) of the filter. A substantial delay (507) is then introduced and the output signal of the last stage is converted into a digital signal over several bits. The digital signal is injected into the feedback loop (108) of said channel and the digital signal is converted into a feedback signal.
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公开(公告)号：EP1046233B1
公开(公告)日：2004-05-19
申请号：EP99947340.8
申请日：1999-09-14
发明人： ALI, Danish
摘要： A radio receiver comprises an input (10) coupled to first and second quadrature related low-IF frequency translation stages (20, 21) generating IF signals at substantially half the channel bandwidth or channel spacing. The IF signals which may be optionally filtered in a pre-filter (28), for example a polyphase filter, are applied to first and second cross-coupled continuous time, low pass Sigma-Delta modulators (30) comprising for example transconductor-capacitor integrators, all but the first integrators of which are cross-coupled by gyrators set to resonate at the IF frequency. Outputs of the Sigma-Delta modulators (30) comprise 1 bit oversampled signals. The oversampled signals in one embodiment are filtered in first decimation stages (32, 34) which provide anti-aliasing. The decimated signals are derotated (38, 40) and decimated in a second decimation means (42, 44) to provide outputs at base band. The outputs are equalised and demodulated to provide an output (48). The input signal may be frequency translated to zero IF and then filtered in low pass filters.
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公开(公告)号：EP1212838B1
公开(公告)日：2003-01-29
申请号：EP00944647.7
申请日：2000-06-12
申请人： ATMEL CORPORATION
发明人： MORIN, Marc, A.
摘要： A delta-sigma modulator (325) having a downconverter mixer circuit (30) in the forward path of the modulator circuit and an upconverter mixer (38) in the feedback path of the modulator. The modulator (325) consists of a loop filter having two components, a bandpass filter (28) before the downconverter (30) and a low-pass filter (32, 33) after the down-converter. The mixer circuits can be implemented as single-sideband rejection mixers with in-phase and quadrature paths. In such a modulator, the loop filter component after the quadrature mixer include two low-pass filters (32, 33), one for the in-phase forward path and another for the quadrature forward path. The feedback also has two paths, which are recombined in the quadrature upconverter (38) located prior to the DAC (50) which produces a real, analog signal (23) to be fed back to the input. Multiple arrangements of this type of modulator can be implemented, including arrangements having multiple intermediate feedback paths to both the baseband low-pass filter and the bandpass loop filter sections.
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公开(公告)号：EP0993123A3
公开(公告)日：2002-01-30
申请号：EP99307670.2
申请日：1999-09-29
摘要： A subtraction section (103) subtracts a first signal from a second signal as a harmonic signal and outputs a third signal as a subtraction result. A first conversion section (105, 106, 107, 108) converts the third signal into a digital signal of predetermined frequency different from a frequency of the second signal. A second conversion section (109, 110, 111, 113) converts the digital signal into an analog signal of a frequency nearly equal to the frequency of the second signal and supplies the analog signal as the first signal to the subtraction section (103). The second conversion section (109, 110, 111, 113) includes a plurality of conversion elements, a filter to calculate a number of use of each of the plurality of conversion elements, and a selector (113) to select the conversion elements having a lower value of the number of use. The number of conversion elements selected corresponds to the value of the digital signal.
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公开(公告)号：EP1103100A1
公开(公告)日：2001-05-30
申请号：EP99934701.6
申请日：1999-07-15
发明人： LIPKA, Dietmar
IPC分类号： H03M3/02 , H04L27/233
CPC分类号： H03D3/007 , H03M3/40 , H03M3/43 , H04L27/2332
摘要： A radio frequency signal is received by using a sigma-delta analog-to-digital converter to sample the radio frequency signal at a sampling rate and to generate therefrom 1-bit digital samples representing a digital intermediate frequency signal. The intermediate frequency signal is demodulated to generate in-phase and quadrature samples. Demodulation may be performed by generating a first mixed signal by combining the 1-bit digital samples representing the intermediate frequency signal with a first sequence representing a cosine mixing signal; generating a second mixed signal by combining the 1-bit digital samples representing the intermediate frequency signal with a second sequence representing a sine mixing signal; and decimating the first and second mixed signals to generate the in-phase and quadrature samples. In alternative embodiments, the intermediate frequency signal is directly converted to in-phase and quadrature signals by using bandpass decimation filtering to subsample two time-shifted sequences of the intermediate frequency. In another alternative, the sigma-delta analog-to-digital converter uses subsampling to convert the radio frequency signal to a first intermediate frequency, and a decimation filter is used to further convert the signal to a second intermediate frequency. An IQ demodulator then reconstructs the in-phase and quadrature signals from the second intermediate frequency signal.
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8.发明公开
公开(公告)号：EP2786542A1
公开(公告)日：2014-10-08
申请号：EP12808702.0
申请日：2012-12-04
申请人： RWTH Aachen
CPC分类号： H04B1/0039 , H03M3/40 , H03M3/50 , H03M7/3028 , H04L27/2053 , H04L27/2092 , H04L27/362
摘要： The invention relates to a transmitter front-end device for generating output signals which constitute a digital stream. The device has at least one first input for a first input signal and at least one second input for a second input signal. The first input signal and the second input signal represent a complex data signal of the digital stream and are to influence an output signal of the transmitter front-end device. The transmitter front-end device further has at least one phase generating device which generates at least one additional phase signal on the basis of the first input signal and the second input signal, at least three phase signals with different phases relative to one another being output by the phase generating device, and at least one modulator which is designed so as to generate a complementary phase signal pair from an obtained phase signal, each of the at least three phase signals being processed into a corresponding complementary phase signal pair by an assigned modulator. The transmitter front-end device further has at least one frequency converter which is designed so as to convert phase signals of a complementary phase signal pair with a high-frequency signal in order to form an output signal.
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9.发明授权Rf signal generation device with configurable sigma-delta modulator and pulse-width modulator for output frequency band selection, and associated methods 有权具有可配置的Σ-Δ调制器的RF信号产生装置和脉冲宽度调制器到输出频带选择和相关程序
公开(公告)号：EP2398148B1
公开(公告)日：2013-01-16
申请号：EP10305659.4
申请日：2010-06-21
申请人： Alcatel Lucent
发明人： Dartois, Luc
CPC分类号： H03M3/396 , H03F3/19 , H03M3/40 , H03M3/402 , H03M3/506 , H04L25/4902 , H04L27/361
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10.发明公开Rf signal generation device with configurable sigma-delta modulator and pulse-width modulator for output frequency band selection, and associated methods 有权具有可配置的Σ-Δ调制器的RF信号产生装置和脉冲宽度调制器到输出频带选择和相关程序
公开(公告)号：EP2398148A1
公开(公告)日：2011-12-21
申请号：EP10305659.4
申请日：2010-06-21
申请人： Alcatel Lucent
发明人： Dartois, Luc
CPC分类号： H03M3/396 , H03F3/19 , H03M3/40 , H03M3/402 , H03M3/506 , H04L25/4902 , H04L27/361
摘要： A RF signal generation device (GD) comprises i) a digital sigma-delta modulator (SM) arranged for modulating a digital signal to output a modulated digital signal of m quantization bits, ii) a transform means (TM) arranged for up-sampling and up-converting this modulated multi bits digital signal from a base frequency band to a radio frequency band at a working sampling frequency, iii) a pulse-width modulator (PM) arranged for transforming this modulated, up-sampled and up-converted digital signal, at this working sampling frequency and by means of n states, into an analog RF signal comprised into an output frequency band, and iv) a clock means (CM) arranged for defining the working sampling frequency. The clock means (CM), digital sigma-delta modulator (SM) and pulse-width modulator (PM) are configurable by means of control commands in order the working sampling frequency varies in an opposite manner to the number m of quantization bits and number n of states as a function of a chosen output frequency band.
摘要翻译： RF信号产生装置（DG）包括：i），被布置用于调制的数字信号，以输出m个量化位的调制的数字信号的数字Σ-Δ调制器（SM），ⅱ）反式构型的装置（TM），被布置用于上采样 和上变换从基频绑带在一个工作采样频率，ⅲ）一个脉冲宽度调制器（PM），设置用于变换该调制，上采样和上变频数字射频此调制的多比特数字信号 信号，在该工作采样频率和由n个状态的手段，进到布置用于工作定义的采样频率的模拟RF信号转换成由输出频带的，和iv）时钟装置（CM）。 时钟装置（CM），数字Σ-Δ调制器（SM）和脉冲宽度调制器（PM）是可配置的由控制命令的装置，以便在工作采样频率变化在上相反的方式来量化位和数目的数目m 状态的N作为选择的输出频率带的功能。
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