公开(公告)号：EP2176954A4

公开(公告)日：2012-10-24

申请号：EP08794200

申请日：2008-08-11

Applicant: UNIV SINGAPORE

Inventor： YU RUI ,  XU YONG PING

IPC: H03M3/00

CPC classification number: H03M3/408 ,  H03M3/434 ,  H03M3/454

公开(公告)号：EP2684292A1

公开(公告)日：2014-01-15

申请号：EP12710885.0

申请日：2012-03-01

Applicant: PGS Geophysical AS

Inventor： HAASL, Sjoerd ,  HEDENSTIERNA, Nils ,  ANDERSSON, Gert ,  WESTBERG, David ,  CARLSSON, Mats

IPC: H03M3/02

CPC classification number: H03M3/434 ,  H03M3/452 ,  H03M3/454

Abstract: A modulator is provided in operative engagement with a sensor element having a plurality of electrodes. The modulator has a single-bit quantizer electrically connected to a digital accumulator. The accumulator accumulates output information received from the single-bit quantizer. The accumulator converts the accumulated output information received from the single-bit quantizer to a multi-bit feedback signal and sends the multi-bit feedback signal in a primary feedback loop back to the sensor element. The quantizer sends a single-bit feedback signal in a secondary feedback loop back to a point before the quantizer.

公开(公告)号：EP2176954A1

公开(公告)日：2010-04-21

申请号：EP08794200.9

申请日：2008-08-11

Applicant: National University of Singapore

Inventor： YU, RUI ,  XU, YONG PING

IPC: H03M3/00

CPC classification number: H03M3/408 ,  H03M3/434 ,  H03M3/454

Abstract: The present invention relates broadly to a system and method for bandpass sigma-delta modulation. The continuous time bandpass sigma-delta modulator comprises an electromechanical filter, a quantizer coupled to an output from the electromechanical filter; and a feedback circuit coupled between an output from the quantizer and an input of the electromechanical filter.

公开(公告)号：EP0297503A3

公开(公告)日：1991-10-02

申请号：EP88110282.6

申请日：1988-06-28

Applicant: NEC CORPORATION

Inventor： Kuraishi, Yoshiaki

IPC: H03M1/50 ,  H03M3/02

CPC classification number: H03M3/47 ,  H03M3/434 ,  H03M3/464

Abstract: The oversampling A/D converter samples an input analog signal at a higher frequency than the frequency band thereof and converts it into a digital signal. It is comprised of a first and second sample and hold means for alternately sampling and holding said input analog signal and generating first and second sample signals. First and second D/A converting means (12, 13) convert first and second digital local signals into corresponding first and second analog local signals, respectively. The respective differences between said first and second sample signals on the one hand and said first and second analog local signals on the other are determined by first and second subtracting means which generate first and second difference signals. Said first and second difference signals are alternately selected by selecting means (7) and delivered to integrating means (8). An integrated signal is supplied to quantizing means (9) which generate a quantized signal. Control logic circuit means (10) generate a digital signal based on said quantized signal. Distributing means (11) distribute said digital signal alternately to said D/A converters (12, 13) as said first and second digital local signals. The present converter makes it possible to achieve about twice as fast operation as the conventional oversampling A/D converters by providing and alternately operating two each of sample and hold circuits, subtracters and D/A converters.

公开(公告)号：EP3143697A1

公开(公告)日：2017-03-22

申请号：EP15721729.0

申请日：2015-05-13

Applicant: Elmos Semiconductor Aktiengesellschaft

Inventor： SUNTKEN, Artur Wilhelm

IPC: H03M3/00

CPC classification number: H03M3/392 ,  H03M3/34 ,  H03M3/434

Abstract: To convert an analogue signal (TP[i]), such as a voltage read signal from a radiation detector, analogue signals (TP[i]) of different size are successively applied to the input of a delta/sigma converter, it being assumed that the analogue signals (TP[i]) each remain essentially unchanged for the duration of the relevant read intervals. A single-bit analogue/digital converter in the form of a quantizer (CMP) with a regulator (ADCFB) connected in series therewith is used to generate a multibit digital signal (SB). To produce an analogue return signal (S8), this multibit digital signal is converted back into an analogue signal. The difference between the analogue signal (TP[i]) to be converted and the analogue return signal (S8) is subjected to low-pass filtering. The regulator (ADCFB) can operate in either of two modes. In a first mode of operation, it corrects target value/actual value discrepancies faster than in its second mode of operation. At the beginning of a read interval, the regulator (ADCFB) operates in the first mode of operation; it then operates in the second mode of operation for the remainder of the read interval.

Abstract translation: 转换成模拟信号（TP [1]）：如从辐射检测器的电压读出信号，模拟信号（TP [1]）不同大小的连续地加到增量/Σ转换器的输入端，它被假定 做了模拟信号（TP [1]）的每个保持用于相关读取间隔的持续时间基本不变。 在量化器（CMP）以串联连接有一个调节器（ADCFB）形式的单比特模拟/数字转换器被用于产生一个多比特数字信号（SB）。 为了生产上的模拟返回信号（S8），该多比特数字信号被转换回上的模拟信号。 模拟信号（TP [1]）之间的差值被转换和模拟返回信号（S8）进行低通滤波。 调节器（ADCFB）可以以两种模式进行操作。 在操作的第一模式中，其校正目标值/比在其第二操作模式快的实际值的差异。 在读取间隔的开始时，调节器（ADCFB）操作在所述第一操作模式; 它然后操作在操作的用于读出间隔的剩余部分的第二模式。

公开(公告)号：EP2203214B1

公开(公告)日：2015-02-25

申请号：EP08794742.0

申请日：2008-07-25

Applicant: MEDTRONIC, INC.

Inventor： TERRY, Michael, B. ,  HEINKS, Michael, W. ,  ANDERSON, Joel, A. ,  FRIGAARD, Mark, A.

IPC: A61N1/37 ,  H03M3/02 ,  H03M3/04

CPC classification number: A61N1/3704 ,  H03M3/34 ,  H03M3/37 ,  H03M3/434

公开(公告)号：EP1784918B1

公开(公告)日：2011-02-09

申请号：EP05779768.0

申请日：2005-08-10

Applicant: Microchip Technology Incorporated

Inventor： DEVAL, Philippe

IPC: H03M3/02

CPC classification number: H03M3/434 ,  H03M3/456

Abstract: A five-level feed-back digital-to-analog converter (DAC) in a switched capacitor sigma-delta analog-to-digital converter has an improved switching sequence that boosts from two to five the number of quantization levels of the feed-back DAC. Switching sequences are used to obtain five equally distributed charge levels C * VREF, C * VREF/2, 0, -C * VREF/2 and -C * VREF. When summed with an input voltage, VIN, the five-level feed­back DAC produces five equally distributed output voltages of A * VIN + VREF, A * VIN + VREF/2, A * VIN + 0, A * VIN - VREF/2 and A * VIN - VREF, where A is gain, VIN is the input voltage, and VREF is the reference voltage.

公开(公告)号：EP0297503B1

公开(公告)日：1995-09-20

申请号：EP88110282.6

申请日：1988-06-28

Applicant: NEC CORPORATION

Inventor： Kuraishi, Yoshiaki

IPC: H03M1/50 ,  H03M3/02

CPC classification number: H03M3/47 ,  H03M3/434 ,  H03M3/464

公开(公告)号：EP2207593B1

公开(公告)日：2015-06-17

申请号：EP08834339.7

申请日：2008-09-25

Applicant: MEDTRONIC, INC.

Inventor： TAN, Wenxiao ,  ANDERSON, Joel A. ,  HEINKS, Michael W.

IPC: A61N1/37 ,  H03M1/12

CPC classification number: H03M3/366 ,  A61N1/3706 ,  A61N1/3718 ,  H03M3/434

公开(公告)号：EP2421156A2

公开(公告)日：2012-02-22

申请号：EP11177593.8

申请日：2011-08-15

Applicant: NXP Semiconductors B.V.

Inventor： Dijkmans, Carl ,  van Beldhoven, Robert H ,  Kup, Bernardus Martinus ,  Neuteboom, Harry ,  van der Dussen, Leon

IPC: H03M3/02

CPC classification number: H03M3/434 ,  H03M3/452

Abstract: A low power, high dynamic range sigma-delta modulator comprises a quantizer followed by a digital integrator for generating an integrated digital signal from a quantized signal. The output of the digital integrator is coupled to a digital-to-analog converter in the feedback loop of the sigma-delta modulator.

Abstract translation: 低功率，高动态范围的Σ-Δ调制器包括量化器，随后是数字积分器，用于从量化信号产生积分数字信号。 数字积分器的输出耦合到Σ-Δ调制器的反馈环路中的数模转换器。