公开(公告)号：EP2539898A4

公开(公告)日：2016-03-30

申请号：EP11746777

申请日：2011-02-07

申请人： CONVERSANT INTELLECTUAL PROPERTY MAN INC

发明人： GILLIGHAM PETER

IPC分类号： G11C11/409 ,  G06F1/32 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  H01L23/00 ,  H01L25/065 ,  H01L27/108

CPC分类号： G06F13/4234 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3253 ,  G06F1/3275 ,  G06F1/3287 ,  G06F13/1689 ,  G11C7/1072 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235 ,  Y02B60/1278 ,  Y02B60/1282 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/17 ,  Y02D10/171 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A semiconductor memory device including a plurality of memory die and a controller die. The controller die is connected to an internal control bus. The controller die is configured to provide to a selected one of the memory die an internal read command responsive to an external read command. The selected memory die is configured to provide read data to the controller in response to the internal read command; wherein latency between receipt by the controller die of the external read command and receipt of the read data from the selected memory die differs for at least two of the memory die when selected as the selected memory die.